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公开(公告)号：US20190319617A1
公开(公告)日：2019-10-17
申请号：US16375233
申请日：2019-04-04
Applicant: STMicroelectronics S.r.l.
IPC: H03K17/687 , H03K17/16 , G01R19/00
Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.
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公开(公告)号：US20180102922A1
公开(公告)日：2018-04-12
申请号：US15601299
申请日：2017-05-22
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Nizza , Roberto Aletti , Francesco Pulvirenti , Giuseppe Cantone
CPC classification number: H04L25/0266 , H04B1/1607 , H04B1/38 , H04B1/581 , H04B3/04 , H04B3/46 , H04B3/56 , H04B2001/0425 , H04L25/085
Abstract: A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n−1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.
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公开(公告)号：US20170141775A1
公开(公告)日：2017-05-18
申请号：US15163142
申请日：2016-05-24
Applicant: STMicroelectronics S.R.L.
Inventor： Giovanni Caggegi , Francesco Pulvirenti , Giuseppe Cantone , Vincenzo Palumbo
IPC: H03K17/687 , H01L29/78 , H03K5/24
CPC classification number: H03K17/687 , H01L29/7816 , H03K5/24 , H03K17/04123 , H03K17/063 , H03K17/74 , H03K2017/066
Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.
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14.发明授权公开(公告)号：US09237039B2
公开(公告)日：2016-01-12
申请号：US14307098
申请日：2014-06-17
Applicant: STMICROELECTRONICS S.r.l.
CPC classification number: H04L25/0292 , H02H9/04 , H04B3/00 , H04L25/028 , Y10T29/49169
Abstract: A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.
Abstract translation: 收发器可连接至具有至少三根电线的电缆。 收发器可以包括受控的输出级，包括高侧支路，具有耦合在输出引脚和正电源引脚之间的具有串联耦合并具有公共电流端子的两个P型晶体管。 P型晶体管具有耦合到高侧支腿的公共电流端子的主体区域。 低侧支腿包括串联耦合并具有公共电流端子的两个N型晶体管，耦合在输出引脚和负电源引脚之间。 N型晶体管具有耦合到低侧支腿的公共电流端子的主体区域。 保护电路还包括耦合在公共电流端子之间的电压钳位器。
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公开(公告)号：US10720921B2
公开(公告)日：2020-07-21
申请号：US16375233
申请日：2019-04-04
Applicant: STMicroelectronics S.r.l.
IPC: H02M3/337 , H03K17/687 , G01R19/00 , H03K17/16
Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.
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Patent Agency Ranking
公开(公告)号：US10110399B2
公开(公告)日：2018-10-23
申请号：US15601299
申请日：2017-05-22
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Nizza , Roberto Aletti , Francesco Pulvirenti , Giuseppe Cantone
Abstract: A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n−1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.
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公开(公告)号：US20180159317A1
公开(公告)日：2018-06-07
申请号：US15596465
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Bruno Mirabella , Francesco Pulvirenti , Salvatore Pappalardo
Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
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公开(公告)号：US20230040189A1
公开(公告)日：2023-02-09
申请号：US17959785
申请日：2022-10-04
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Giovanni Fontana , Marco Riva , Francesco Pulvirenti , Giuseppe Cantone
IPC: H03K17/06 , H03K17/0812
Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.
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公开(公告)号：US11476845B2
公开(公告)日：2022-10-18
申请号：US17355055
申请日：2021-06-22
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Giovanni Fontana , Marco Riva , Francesco Pulvirenti , Giuseppe Cantone
IPC: H03K5/151 , H03K17/16 , H03K17/687 , H03K17/06 , H03K17/0812
Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.
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公开(公告)号：US10084446B2
公开(公告)日：2018-09-25
申请号：US15163142
申请日：2016-05-24
Applicant: STMicroelectronics S.R.L.
Inventor： Giovanni Caggegi , Francesco Pulvirenti , Giuseppe Cantone , Vincenzo Palumbo
IPC: H03K17/687 , H01L29/78 , H03K5/24 , H03K17/0412 , H03K17/06 , H03K17/74
CPC classification number: H03K17/687 , H01L29/7816 , H03K5/24 , H03K17/04123 , H03K17/063 , H03K17/74 , H03K2017/066
Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.
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