公开(公告)号：US20190035728A1

公开(公告)日：2019-01-31

申请号：US16044190

申请日：2018-07-24

Applicant: STMicroelectronics S.r.l.

Inventor： Ivan Venegoni ,  Francesca Milanesi ,  Francesco Maria Pipia ,  Samuele Sciarrillo ,  Paolo Colpani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An integrated device includes a semiconductor body and a dielectric layer bounded by a surface. A conductive region of a first metal material forms a via region extending into a hole passing through the dielectric layer, and an overlaid redistribution region which extends over the surface. At least one barrier region of a second metal material extends into the hole and surrounds the via region, and the barrier region furthermore extending over the surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the surface. A second coating layer of a fourth metal material extends at a distance from the surface and covers the first coating layer, and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier region extending over the surface.

公开(公告)号：US20190035727A1

公开(公告)日：2019-01-31

申请号：US16044186

申请日：2018-07-24

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Maria Pipia ,  Ivan Venegoni ,  Annamaria Votta ,  Francesca Milanesi ,  Samuele Sciarrillo ,  Paolo Colpani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

公开(公告)号：US09960131B2

公开(公告)日：2018-05-01

申请号：US15251355

申请日：2016-08-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Paolo Colpani ,  Antonella Milani ,  Lucrezia Guarino ,  Andrea Paleari

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/50 ,  H01L23/522 ,  H01L23/562 ,  H01L24/00 ,  H01L24/03 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05655 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/351

Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.

公开(公告)号：US20170221841A1

公开(公告)日：2017-08-03

申请号：US15251355

申请日：2016-08-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Paolo Colpani ,  Antonella Milani ,  Lucrezia Guarino ,  Andrea Paleari

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/50 ,  H01L23/522 ,  H01L23/562 ,  H01L24/00 ,  H01L24/03 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05655 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/351

Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.