公开(公告)号：US20160133754A1

公开(公告)日：2016-05-12

申请号：US14661470

申请日：2015-03-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Keon MOON ,  Masataka KANO ,  Sung-Hoon YANG ,  Ji Hun LIM ,  So Young KOO ,  Myoung Hwa KIM ,  Jun Hyung LIM

IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/66

CPC classification number: H01L29/78645 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract translation: 薄膜晶体管衬底包括衬底，衬底上的底栅，衬底上的第一绝缘层和底栅，第一绝缘层上的漏极，第一绝缘层上的源，源包括第一绝缘层 漏极的第一侧的源极和在漏极的第二侧的第二源极，在第一绝缘层上的有源层，有源层包括接触漏极和第一源极的第一有源层和与第一源极接触的第二有源层 漏极和第二源极，漏极，源极和有源层上的第二绝缘层，以及第二绝缘层上的顶栅极。

公开(公告)号：US20190312061A1

公开(公告)日：2019-10-10

申请号：US16371433

申请日：2019-04-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kyoung Seok SON ,  Myounghwa KIM ,  Jaybum KIM ,  Yeon Keon MOON ,  Masataka KANO

IPC: H01L27/12 ,  H01L27/32

Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.

公开(公告)号：US20160365368A1

公开(公告)日：2016-12-15

申请号：US14963769

申请日：2015-12-09

Applicant: Samsung Display Co., Ltd.

Inventor： Masataka KANO ,  Ji Hun LIM ,  Yeon Keon MOON ,  Jun Hyung LIM ,  So Young KOO ,  Myoung Hwa KIM

IPC: H01L27/12 ,  H01L29/788 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/1248 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788

Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.

Abstract translation: 薄膜晶体管阵列面板包括基板，设置在基板上的第一栅极电极，设置在第一栅电极上的第一自组装单层，设置在第一自组装单层上的栅极绝缘层，设置在第一自组装单层上的半导体 所述栅极绝缘层，与所述半导体重叠的漏电极，所述漏电极相对于所述半导体分离并面对源电极，设置在所述源电极和所述漏电极上的第一层间绝缘层，第二自组装单层 设置在第一层间绝缘层上的第二栅电极，设置在第二自组装单层上的第二栅电极，设置在第二栅电极上的第二层间绝缘层，以及设置在第二层间绝缘层上并连接到漏极的像素电极 。

公开(公告)号：US20160210926A1

公开(公告)日：2016-07-21

申请号：US14862388

申请日：2015-09-23

Applicant: Samsung Display Co., Ltd.

Inventor： Tadashi AMINO ,  Jong Hee KIM ,  Masataka KANO ,  Jun Hyun PARK

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G11C19/184 ,  G11C19/28 ,  H01L27/124 ,  H01L27/1255

Abstract: A Rate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.

Abstract translation: A速率驱动电路包括：多个阶段向栅线输出信号，该级包括一端和控制端连接的第一晶体管，一端与控制端与第一输入端连接，另一端 端部连接到第二节点，第二晶体管包括连接到与时钟输入端子连接的第一节点的控制端子，以及连接到第一输出端子的另一端，其一端连接到第一节点的第一电容器 第一节点，另一端连接到第二晶体管和第一输出端子的另一端，第三晶体管的一端连接到第一晶体管的另一端，另一端与第一节点连接 并且控制终端连接到第三节点。