公开(公告)号：US20200272478A1

公开(公告)日：2020-08-27

申请号：US16462086

申请日：2017-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok KWON ,  Jae-un PARK ,  Dong-kwan SUH ,  Kang-jin YOON

IPC: G06F9/38 ,  G06F9/30

Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.

公开(公告)号：US20190147319A1

公开(公告)日：2019-05-16

申请号：US16163772

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava PRASAD ,  Dae-hyun KIM ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06N3/04 ,  G06F17/15 ,  G06N5/04 ,  G06F12/06 ,  G06F21/52

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

公开(公告)号：US20180101357A1

公开(公告)日：2018-04-12

申请号：US15727093

申请日：2017-10-06

Applicant: Samsung Electronics Co ., Ltd .

Inventor： Jae-un PARK ,  Jong-hun LEE ,  Ki-seok KWON ,  Dong-kwan SUH ,  Kang-jin YOON ,  Jung-uk CHO

IPC: G06F5/06 ,  G06F13/16 ,  G06F9/52 ,  G06F9/38

CPC classification number: G06F5/065 ,  G06F9/3855 ,  G06F9/52 ,  G06F13/1673

Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.

公开(公告)号：US20170123658A1

公开(公告)日：2017-05-04

申请号：US15090111

申请日：2016-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Young-hwan PARK

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F12/00

Abstract: Methods and apparatuses for parallel processing data include reading items of data from a memory by using a memory access address, confirming items of data that have the same memory address from among the read items of data, masking items of data other than one from among the confirmed items of data, generating a correction value by using the confirmed items of data, performing an operation by using the items of data and the correction value, and storing, in the memory, data obtained by operating the data that has not been masked.

公开(公告)号：US20170017610A1

公开(公告)日：2017-01-19

申请号：US15039603

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Chul-soo PARK

IPC: G06F15/78 ,  G06F15/82

CPC classification number: G06F15/7871 ,  G06F1/3225 ,  G06F15/82

Abstract: A technology for controlling a reconfigurable processor is provided. A determination is made as to whether configuration information is provided from a configuration buffer in a preset process performed by the reconfigurable processor, based on address values of the configuration information that are stored in the configuration buffer. Therefore, access to a configuration memory is controlled to reduce power consumption.

Abstract translation: 提供了一种用于控制可重构处理器的技术。 根据存储在配置缓冲器中的配置信息的地址值，确定在由可重配置处理器执行的预设处理中是否从配置缓冲器提供配置信息。 因此，控制对配置存储器的访问以降低功耗。