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公开(公告)号：US20210066276A1
公开(公告)日：2021-03-04
申请号：US16806030
申请日：2020-03-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho KIM , Dongku KANG , Daeseok BYEON
Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210036008A1
公开(公告)日：2021-02-04
申请号：US16809059
申请日：2020-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwa YUN , Chanho KIM , Dongku KANG
IPC: H01L27/11582 , H01L27/11565
Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.
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13.发明申请NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF 有权包含页面缓冲器的非易失性存储器件及其操作方法公开(公告)号：US20140153329A1
公开(公告)日：2014-06-05
申请号：US14077606
申请日：2013-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongku KANG , Dae Yeal LEE
CPC classification number: G11C16/3459 , G11C7/1039 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3481 , G11C17/06
Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.
Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。
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公开(公告)号：US20220208784A1
公开(公告)日：2022-06-30
申请号：US17695186
申请日：2022-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwa YUN , Pansuk KWAK , Chanho KIM , Dongku KANG
IPC: H01L27/11573 , H01L27/1157 , G11C16/08 , G11C7/18 , H01L27/11524 , H01L27/11519 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/11582
Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.
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公开(公告)号：US20210366892A1
公开(公告)日：2021-11-25
申请号：US17393934
申请日：2021-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho KIM , Dongku KANG , Daeseok BYEON
Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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Patent Agency Ranking
公开(公告)号：US20210161034A1
公开(公告)日：2021-05-27
申请号：US16952595
申请日：2020-11-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chihwan JEONG , Kyungha KOO , Jihong KIM , Dongku KANG , Kuntak KIM , Yunjeong PARK , Kyuhwan LEE , Haejin LEE , Seyoung JANG , Hyuntae JANG
Abstract: The disclosure relates to a wireless charging device including a cooling fan, and the wireless charging device according to an embodiment of the disclosure includes: a housing including a holding portion configured to hold an external electronic device; a first bracket positioned in the holding portion; a conductive coil disposed in the first bracket; a second bracket positioned in the holding portion and including a penetrating hole; a first cooling fan positioned in the penetrating hole; a second cooling fan positioned in the penetrating hole and spaced apart from the first cooling fan; and a partition formed in the penetrating hole to isolate the first cooling fan and the second cooling fan from each other, the penetrating hole being divided into a first area having the first cooling fan disposed therein and a second area having the second cooling fan positioned therein, at least one protrusion having a volute shape formed on at least a portion of the second bracket or at least a portion of the partition, a first opening formed on at least an area of the first bracket to allow air cooled by the first cooling fan and/or the second cooling fan to move to the holding portion, and a second opening formed on at least an area of the holding portion to allow the air transmitted from the first opening to move outside the wireless charging device.
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公开(公告)号：US20210118861A1
公开(公告)日：2021-04-22
申请号：US16940333
申请日：2020-07-27
Applicant: SAMSUNG ELECTRONICS CO, LTD.
Inventor： Kyunghwa YUN , Chanho KIM , Dongku KANG
IPC: H01L25/18 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L25/065 , H01L23/00
Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US20210066320A1
公开(公告)日：2021-03-04
申请号：US16944733
申请日：2020-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho KIM , Dongku KANG , Daeseok BYEON
IPC: H01L27/112 , H01L27/24 , H01L27/108 , H01L27/11585
Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210043641A1
公开(公告)日：2021-02-11
申请号：US17001035
申请日：2020-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwa YUN , Pansuk KWAK , Chanho KIM , Dongku KANG
IPC: H01L27/11573 , H01L27/1157 , G11C16/08 , G11C7/18 , H01L27/11582 , H01L27/11519 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/11524
Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.
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公开(公告)号：US20160300601A1
公开(公告)日：2016-10-13
申请号：US15188461
申请日：2016-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongku KANG
CPC classification number: G11C7/12 , G11C7/065 , G11C16/10 , G11C16/24 , G11C16/3459
Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.
Abstract translation: 一种非易失性存储装置的编程方法包括将要存储在连接到第一字线的第一存储单元中的第一字线数据和要存储在连接到第二字线的第二存储单元中的第二字线数据进行加载; 根据第一字线数据设置高位线; 在高位线建立之后关闭位线共享晶体管; 根据第二字线数据设置较低位线; 使用高位线对所述第一存储器单元执行第一编程操作; 打开位线共享晶体管; 以及使用所述下位线对所述第二存储器单元执行第二编程操作。 位线共享晶体管响应于位线共享信号而电连接高位线和低位线。
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