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公开(公告)号：US20230008679A1
公开(公告)日：2023-01-12
申请号：US17862205
申请日：2022-07-11
发明人： Yunjeong PARK , Kyungha KOO , Dongku KANG , Jihong KIM , Haein CHUNG
摘要： Various embodiments of the disclosure relate to a heat radiating structure and an electronic device including the same. According to various embodiments of the disclosure, it is possible to provide an electronic device including: a housing including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a third surface enclosing an internal space between the first surface and the second surface, wherein at least one portion of the third surface faces a third direction different from the first direction and the second direction, wherein a first opening is formed in the first surface, and a second opening is formed in the third surface; a substrate disposed in the internal space; an electronic component disposed on at least one surface of the substrate; and a mesh member disposed in the internal space and disposed adjacent to the first opening and the second opening.
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公开(公告)号：US20130088923A1
公开(公告)日：2013-04-11
申请号：US13688249
申请日：2012-11-29
发明人： Dongku KANG
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5621
摘要： A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data.
摘要翻译： 一种对非易失性存储器件进行编程的方法包括：基于较低位数据选择性地将存储器单元从第一状态编程到第二状态，有选择地将存储器单元从第二状态编程到对应于较低位数据的中间状态，以及选择性编程 存储单元基于高位数据从中间状态到第三或第四状态。
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3.发明公开公开(公告)号：US20230156965A1
公开(公告)日：2023-05-18
申请号：US18099522
申请日：2023-01-20
发明人： Haein CHUNG , Kyungha KOO , Dongku KANG , Kangsik KIM , Wonmin KIM , Jihong KIM , Chihwan JEONG
CPC分类号： H05K7/20336 , H04M1/0283
摘要： Disclosed is a heat-dissipating structure comprising: a case including: a first body and a second body spaced apart from each other; a wick disposed in a space between the first body and the second body, the wick including a plurality of wires arranged in a first direction and in a second direction intersecting the first direction, and having a working fluid passage formed along at least one opening formed between the plurality of wires; and a channel formed between the first body and the wick and in which the working fluid is moved through the at least one opening according to a change in state of the working fluid.
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公开(公告)号：US20220171434A1
公开(公告)日：2022-06-02
申请号：US17564773
申请日：2021-12-29
发明人： Jinyong PARK , Dongku KANG , Jichul KIM , Bongkyu MIN , Baekeun CHO , Chihyun CHO , Hyuncheol JIN
摘要： An electronic device is provided. The electronic device includes a rollable display. The electronic device may include a main bracket configured to support the first portion of the rollable display, a roller member disposed in the first direction from the main bracket and arranged in a third direction perpendicular to the first direction, at least one folding support member disposed between the main bracket and the roller member and configured to support the second portion of the rollable display, a circuit board disposed to overlap at least a portion of the main bracket, at least one electronic component disposed adjacent to the roller member, and a FPCB configured to electrically connecting the main circuit board and the electronic component, wherein the FPCB is disposed to pass through the folding support member and extends from a portion of the circuit board to a portion of the electronic component.
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公开(公告)号：US20210043639A1
公开(公告)日：2021-02-11
申请号：US16814491
申请日：2020-03-10
发明人： Kyunghwa YUN , Pansuk KWAK , Chanho KIM , Dongku KANG
IPC分类号： H01L27/11556 , G11C5/02 , G11C5/06 , H01L27/11582
摘要： A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.
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公开(公告)号：US20240331785A1
公开(公告)日：2024-10-03
申请号：US18739530
申请日：2024-06-11
发明人： Kyung-Min KANG , Dongku KANG , Su Chang JEON , Won-Taeck JUNG
CPC分类号： G11C16/3481 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30
摘要： A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.
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公开(公告)号：US20230207549A1
公开(公告)日：2023-06-29
申请号：US18179056
申请日：2023-03-06
发明人： Chanho KIM , Dongku KANG , Daeseok BYEON
CPC分类号： H01L25/18 , H01L23/481 , H01L24/08 , H01L2224/05647 , H01L2224/08145 , H01L24/05
摘要： An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210251110A1
公开(公告)日：2021-08-12
申请号：US17166248
申请日：2021-02-03
发明人： Haejin LEE , Dongku KANG , Jihong KIM , Min PARK , Yunjeong PARK , Kyuhwan LEE , Jinhwan JUNG , Ahreum HWANG , Kyungha KOO
摘要： A portable communication device is provided. A portable communication device includes a first nanofiber member having a first density, a second nanofiber member attached to the first nanofiber member and having a second density lower than the first density, a heat transfer member positioned on or above the second nanofiber member, and a conductive material coated on at least a portion of the first nanofiber member and the second nanofiber member. At least some of the conductive material may penetrate into the first nanofiber member or the second nanofiber member. Various other embodiments may be possible.
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9.发明申请NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF 审中-公开包含页面缓冲器的非易失性存储器件及其操作方法公开(公告)号：US20160012907A1
公开(公告)日：2016-01-14
申请号：US14853488
申请日：2015-09-14
发明人： Dongku KANG , Dae Yeal LEE
CPC分类号： G11C16/3459 , G11C7/1039 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3481 , G11C17/06
摘要： A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.
摘要翻译： 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。
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公开(公告)号：US20140219025A1
公开(公告)日：2014-08-07
申请号：US14151534
申请日：2014-01-09
发明人： Dongku KANG
CPC分类号： G11C7/12 , G11C7/065 , G11C16/10 , G11C16/24 , G11C16/3459
摘要： A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.
摘要翻译： 一种非易失性存储装置的编程方法包括将要存储在连接到第一字线的第一存储单元中的第一字线数据和要存储在连接到第二字线的第二存储单元中的第二字线数据进行加载; 根据第一字线数据设置高位线; 在高位线建立之后关闭位线共享晶体管; 根据第二字线数据设置低位线; 使用高位线对所述第一存储器单元执行第一编程操作; 打开位线共享晶体管; 以及使用所述下位线对所述第二存储器单元执行第二编程操作。 位线共享晶体管响应于位线共享信号而电连接高位线和低位线。
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