公开(公告)号：US11538913B2

公开(公告)日：2022-12-27

申请号：US17175850

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Heonjong Shin ,  Sunghun Jung ,  Doohyun Lee ,  Hwichan Jun ,  Hakyoon Ahn

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/285 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20240413216A1

公开(公告)日：2024-12-12

申请号：US18808369

申请日：2024-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim ,  Minchan Gwak ,  Jinyoung Park ,  Hyunho Park

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

公开(公告)号：US12094940B2

公开(公告)日：2024-09-17

申请号：US17546213

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim ,  Minchan Gwak ,  Jinyoung Park ,  Hyunho Park

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/0665

Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

公开(公告)号：US20220216107A1

公开(公告)日：2022-07-07

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11309218B2

公开(公告)日：2022-04-19

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/308 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11264386B2

公开(公告)日：2022-03-01

申请号：US17038435

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US11177362B2

公开(公告)日：2021-11-16

申请号：US16829372

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Minchan Gwak ,  Hyunho Park ,  Sunghun Jung ,  Yongsik Jeong ,  Sangwon Jee ,  Inchan Hwang

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.