公开(公告)号：US20240421216A1

公开(公告)日：2024-12-19

申请号：US18676858

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggyu Han ,  Heonjong Shin ,  Juneyoung Park ,  Sanghee Lee ,  Jaeran Jang ,  Mingi Chung

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated circuit semiconductor device includes a base layer including a first surface and a second surface, a gate structure on the first surface of the base layer, a first source and drain region on a side of the gate structure, a second source and drain region on another side of the gate structure, a first placeholder in the base layer in a lower portion of the first source and drain region and electrically connected to the first source and drain region, a second placeholder in the base layer in a lower portion of the second source and drain region, and a metal power rail on the first placeholder and the second placeholder on the second surface of the base layer and electrically connected to the first placeholder.

公开(公告)号：US20210082757A1

公开(公告)日：2021-03-18

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US20190304973A1

公开(公告)日：2019-10-03

申请号：US16444683

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

公开(公告)号：US11978775B2

公开(公告)日：2024-05-07

申请号：US17841873

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Hyun-Seung Song ,  Yeongchang Roh ,  Heonjong Shin ,  Sora You ,  Yongsik Jeong

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/45

CPC classification number: H01L29/41775 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/456

Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

公开(公告)号：US20230402376A1

公开(公告)日：2023-12-14

申请号：US18095080

申请日：2023-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L23/532 ,  H01L27/082

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/088 ,  H01L23/53295 ,  H01L27/082

Abstract: Semiconductor devices and fabrication methods thereof. For example, a semiconductor device may include a dielectric structure, and first conductive structures and second conductive structures. The dielectric structure may include a first dielectric layer that surrounds the first conductive structures and a second dielectric layer that surrounds the second conductive structures. The first dielectric layer may include a first intervention between the first conductive structures. The second dielectric layer may include a second intervention between the second conductive structures. A width in a first direction of the first intervention may decrease in a second direction from a top surface toward a bottom surface of the first intervention. A width in the first direction of the second intervention may increase in the second direction from a top surface toward a bottom surface of the second intervention. The first dielectric layer and the second dielectric layer may include different dielectric materials.

公开(公告)号：US11335679B2

公开(公告)日：2022-05-17

申请号：US16825030

申请日：2020-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hyun Park ,  Heonjong Shin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.

公开(公告)号：US12014957B2

公开(公告)日：2024-06-18

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/3083 ,  H01L21/32139 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US20240030345A1

公开(公告)日：2024-01-25

申请号：US18112312

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong Shin ,  Seon-Bae Kim ,  Jaeran Jang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/78391 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/6656

Abstract: In some embodiments, the semiconductor device includes a substrate comprising a cell region, a dummy region spaced apart from the cell region in a first direction, and a border region between the cell region and the dummy region, an active pattern on the cell region, a device isolation layer on the substrate, source/drain patterns on the active pattern and channel patterns between the source/drain patterns, cell gate electrodes crossing the channel patterns in a second direction, active contacts disposed on the cell region and between the cell gate electrodes and coupled to the source/drain patterns, dummy gate electrodes on the dummy region and on the device isolation layer, dummy contacts on the dummy region and on a side surface of each of the dummy gate electrodes, an interlayer insulating layer on the side surface of each of the dummy gate electrodes, and a dam structure on the border region.

公开(公告)号：US11735640B2

公开(公告)日：2023-08-22

申请号：US17488443

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Minchan Gwak ,  Hyunho Park ,  Sunghun Jung ,  Yongsik Jeong ,  Sangwon Jee ,  Inchan Hwang

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

公开(公告)号：US11728342B2

公开(公告)日：2023-08-15

申请号：US17659069

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hyun Park ,  Heonjong Shin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/76802

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.