公开(公告)号：US11978775B2

公开(公告)日：2024-05-07

申请号：US17841873

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Hyun-Seung Song ,  Yeongchang Roh ,  Heonjong Shin ,  Sora You ,  Yongsik Jeong

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/45

CPC classification number: H01L29/41775 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/456

Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

公开(公告)号：US12014957B2

公开(公告)日：2024-06-18

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/3083 ,  H01L21/32139 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11735640B2

公开(公告)日：2023-08-22

申请号：US17488443

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Minchan Gwak ,  Hyunho Park ,  Sunghun Jung ,  Yongsik Jeong ,  Sangwon Jee ,  Inchan Hwang

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

公开(公告)号：US20210082757A1

公开(公告)日：2021-03-18

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US08815681B2

公开(公告)日：2014-08-26

申请号：US13679420

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsik Jeong ,  Jeonguk Han ,  Weonho Park ,  Byungsup Shim

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/105 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8239

CPC classification number: H01L21/8239 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.

Abstract translation: 提供了非易失性存储器件及其形成方法，非易失性存储器件可以包括沿着第一方向延伸并且沿与第一方向交叉的第二方向交替地设置在半导体衬底中的第一区域和第二区域。 埋设的掺杂线分别形成在第一区域并沿第一方向延伸。 掩埋掺杂线可以掺杂有第一导电类型的掺杂剂。 掺杂有第二导电类型的掺杂剂的器件区域和器件隔离图案沿第二方向设置。 块区域和器件隔离图案可以形成在第二区域中。 跨越掩埋掺杂线和体区的字线彼此平行地形成。 接触结构连接到掩埋掺杂线并且设置在器件隔离图案之间。

公开(公告)号：US11705454B2

公开(公告)日：2023-07-18

申请号：US17582357

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L29/417 ,  H01L27/02 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/6681 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US10923475B2

公开(公告)日：2021-02-16

申请号：US16391757

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US20220216107A1

公开(公告)日：2022-07-07

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11309218B2

公开(公告)日：2022-04-19

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/308 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11264386B2

公开(公告)日：2022-03-01

申请号：US17038435

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.