公开(公告)号：US20240178229A1

公开(公告)日：2024-05-30

申请号：US18430902

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US11908861B2

公开(公告)日：2024-02-20

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US11764279B2

公开(公告)日：2023-09-19

申请号：US17451691

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nakjin Son ,  Seungjoon Lee ,  Bong Seob Yang ,  Doyoung Choi

IPC: H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/02194 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

公开(公告)号：US20220181323A1

公开(公告)日：2022-06-09

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.