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    METHOD AND APPARATUS FOR PARALLEL CONCATENATED LDPC CONVOLUTIONAL CODES ENABLING POWER-EFFICIENT DECODERS
    12.
    发明申请
    METHOD AND APPARATUS FOR PARALLEL CONCATENATED LDPC CONVOLUTIONAL CODES ENABLING POWER-EFFICIENT DECODERS 审中-公开
    方法和装置并行解决的LDPC转换代码实现功率有效的解码器

    公开(公告)号：US20160164537A1

    公开(公告)日：2016-06-09

    申请号：US14827150

    申请日：2015-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eran Pisek ,  Shadi Abu-Surra

    IPC: H03M13/11 ,  H03M13/29 ,  H03M13/39

    CPC classification number: H03M13/116 ,  H03M13/036 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1154 ,  H03M13/6362

    Abstract: A method of encoding includes receiving input systematic data including an input group (xz(n)) of Z systematic bits. The method includes generating an LDPC base code using the input group (xz(n)). The LDPC base code is characterized by a row weight (Wr), a column weight (Wc), and a first level lifting factor (Z). The method includes transforming the LDPC base code into a Trellis-based Quasi-Cyclic LDPC (TQC-LDPC) convolutional code. The method includes generating a Parallel Concatenated TQC-LDPC convolutional code in a form of an H-matrix including a systematic submatrix (Hsys) of the input systematic data and a parity check submatrix (Hpar) of parity check bits, wherein the Hpar includes a column of Z-group parity bits. The method includes concatenating the Hpar with each column of systematic bits, wherein the Hpar includes J parity bits per systematic bit.

    Abstract translation: 一种编码方法包括接收包括Z个系统比特的输入组（xz（n））的输入系统数据。 该方法包括使用输入组（xz（n））生成LDPC基码。 LDPC基代码的特征在于行权重（Wr），列权重（Wc）和第一级提升因子（Z）。 该方法包括将LDPC码转换为基于网格的准循环LDPC（TQC-LDPC）卷积码。 该方法包括以包括输入系统数据的系统子矩阵（Hsys）和奇偶校验位的奇偶校验子矩阵（Hpar）的H矩阵的形式生成并行级联TQC-LDPC卷积码，其中Hpar包括 Z组奇偶校验位列。 该方法包括将Hpar与每列系统比特串联，其中Hpar包括每个系统比特的J个奇偶校验位。

    METHOD AND APPARATUS TO ENABLE LOW POWER SYNCHRONIZATION FOR LARGE BANDWIDTH WIRELESS LAN SYSTEMS
    13.
    发明申请
    METHOD AND APPARATUS TO ENABLE LOW POWER SYNCHRONIZATION FOR LARGE BANDWIDTH WIRELESS LAN SYSTEMS 审中-公开
    实现大型无线局域网系统的低功耗同步的方法和设备

    公开(公告)号：US20150282068A1

    公开(公告)日：2015-10-01

    申请号：US14579740

    申请日：2014-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sridhar Rajagopal ,  Shadi Abu-Surra ,  Eran Pisek

    IPC: H04W52/02 ,  H04W56/00 ,  H04W28/20

    CPC classification number: H04W52/0206 ,  H04L5/0012 ,  H04L5/0048 ,  H04L5/0064 ,  H04L27/2613 ,  H04L27/2655 ,  H04L27/2666 ,  H04L27/2675 ,  H04L27/2689 ,  H04L27/2692 ,  H04W52/0209 ,  H04W56/00 ,  H04W84/12 ,  Y02D70/00 ,  Y02D70/142

    Abstract: In a packet-based communication system, a transmitter and a receiver implement low power synchronization techniques. The transmitter transmits a packet that includes a two-part preamble. A first part of the two-part preamble is transmitted at a first reduced bandwidth that is smaller than a second bandwidth of the channel, and at least one of a second part of the two-part preamble and another portion of the packet is transmitted at the second bandwidth of the channel. The receiver includes an interleaved analog-to-digital converter (ADC) including multiple sub-ADCs. The receiver turns on a first subset of the multiple sub-ADCs during an idle listening period, and turns on a second subset of the multiple sub-ADCs upon detection of a completion of the first part of the two-part preamble, wherein the first subset of the multiple sub-ADCs is less than the second subset of the multiple sub-ADCs.

    Abstract translation: 在基于分组的通信系统中，发射机和接收机实现低功率同步技术。 发射机发送包括两部分前同步码的分组。 两部分前导码的第一部分以小于该信道的第二带宽的第一减小带宽发送，并且该两部分前导码的第二部分和分组的另一部分中的至少一个以 频道的第二个带宽。 该接收机包括一个包括多个子ADC的交错模数转换器（ADC）。 接收机在空闲监听期间接通多个子ADC的第一子集，并且在检测到两部分前导码的第一部分的完成时，打开多个子ADC的第二子集，其中第一个 多个子ADC的子集小于多个子ADC的第二子集。

    Method and apparatus of QC-LDPC convolutional coding and low-power high throughput QC-LDPC convolutional encoder and decoder
    14.
    发明授权
    Method and apparatus of QC-LDPC convolutional coding and low-power high throughput QC-LDPC convolutional encoder and decoder 有权
    QC-LDPC卷积编码和低功率高吞吐量QC-LDPC卷积编码器和解码器的方法和装置

    公开(公告)号：US08910025B2

    公开(公告)日：2014-12-09

    申请号：US13625656

    申请日：2012-09-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eran Pisek

    IPC: H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1154 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/3746 ,  H03M13/4138 ,  H03M13/6502 ,  H03M13/658

    Abstract: A low-density parity check (LDPC) encoder and input configured to receive an incoming signal stream. The encoder generates, from a block code H-matrix comprising a data portion and a parity check portion, a continuous H-matrix by concatenating the data portion into successive, recurring, data blocks that are separated by a specified symbol interval, and performs LDPC encoding of each data portion using the parity check portion associated with the data portion using its associated parity check portion. Additionally, a Trellis-based low-density parity check (LDPC) decoder configured to receive an encoded stream and decode the received signal to recover the signal stream.

    Abstract translation: 低密度奇偶校验（LDPC）编码器和被配置为接收输入信号流的输入。 编码器从包括数据部分和奇偶校验部分的块代码H矩阵生成连续的H矩阵，将数据部分连接成以指定符号间隔分隔的连续的循环数据块，并执行LDPC 使用其相关联的奇偶校验部分使用与数据部分相关联的奇偶校验部分对每个数据部分进行编码。 另外，基于网格的低密度奇偶校验（LDPC）解码器被配置为接收编码流并对接收到的信号进行解码以恢复信号流。

    XF ERASURE CODE FOR DISTRIBUTED STORAGE SYSTEMS
    16.
    发明申请
    XF ERASURE CODE FOR DISTRIBUTED STORAGE SYSTEMS 审中-公开
    用于分布式存储系统的XF擦除码

    公开(公告)号：US20170046227A1

    公开(公告)日：2017-02-16

    申请号：US15017389

    申请日：2016-02-05

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Xiaoqing Fan ,  Eran Pisek ,  Shadi Abu-Surra

    IPC: G06F11/10 ,  H03M13/15 ,  H04L29/08

    CPC classification number: G06F11/1088 ,  H03M13/1515 ,  H03M13/154 ,  H04L67/1097

    Abstract: An encoding apparatus includes a processor and a communication interface operably coupled to a distributed storage system (DSS) that includes n storage device nodes. The processor is coupled to the communication interface, and configured to encode the nodes according to an XF erasure code by: dividing a number of symbols of original data into k data packets; selecting k of the storage device nodes to store the k data packets and n−k other storage device nodes to store parity packets; outputting the k data packets to the k selected storage device nodes; obtaining an XF code generator matrix; generating n−k parity packets according to a function of the k data packets and the XF code generator matrix; and outputting the n−k parity packets to each of the n−k other storage device nodes.

    Abstract translation: 编码装置包括处理器和可操作地耦合到包括n个存储设备节点的分布式存储系统（DSS）的通信接口。 所述处理器耦合到所述通信接口，并且被配置为根据XF擦除码对所述节点进行编码：将原始数据的符号数量划分为k个数据分组; 选择存储设备节点的k以存储k个数据分组和n-k个其他存储设备节点以存储奇偶校验分组; 将k个数据分组输出到k个选择的存储设备节点; 获得一个XF代码生成器矩阵; 根据k个数据分组和XF代码生成矩阵的函数产生n-k个奇偶分组; 并将n-k个奇偶校验分组输出到每个n-k个其他存储设备节点。

    EFFICIENT MULTIPLY-ACCUMULATE PROCESSOR FOR SOFTWARE DEFINED RADIO
    18.
    发明申请
    EFFICIENT MULTIPLY-ACCUMULATE PROCESSOR FOR SOFTWARE DEFINED RADIO 审中-公开
    用于软件定义无线电的高效多媒体处理器

    公开(公告)号：US20140219374A1

    公开(公告)日：2014-08-07

    申请号：US14033283

    申请日：2013-09-20

    Applicant: Samsung Electronics Co., LTD

    Inventor： Eran Pisek

    IPC: H04L27/26

    CPC classification number: G06F17/142 ,  H04L27/263 ,  H04L27/265

    Abstract: A Fast Fourier Transform (FFT) context-based reconfigurable instruction set processor (CRISP) machine receives N data symbols. The FFT CRISP includes multiply-accumulate (MAC) blocks, each configured to generate two intermediate results of a butterfly algorithm by calculating complex products and sums using the received data symbols and twiddle factors. The FFT CRISP includes a memory configured to store the received data symbols, the twiddle factors, and the intermediate results of the butterfly algorithm. The FFT CRISP includes a configurable instruction set digital signal processor core configured to: select and read a pair of the received data symbols from a location in the memory; input each selected pair of the received data symbols to the MAC blocks; write, to the location, the intermediate results the MAC blocks generated using the selected at least one pair of the N received data symbols; and output N binary symbols.

    Abstract translation: 快速傅里叶变换（FFT）上下文的可重构指令集处理器（CRISP）机器接收N个数据符号。 FFT CRISP包括乘法累加（MAC）块，每个块被配置为通过使用接收到的数据符号和旋转因子计算复杂乘积和求和来生成蝴蝶算法的两个中间结果。 FFT CRISP包括被配置为存储接收到的数据符号的存储器，旋转因子和蝴蝶算法的中间结果。 FFT CRISP包括可配置指令集数字信号处理器核心，其被配置为：从存储器中的位置选择和读取一对所接收的数据符号; 将所选择的一对接收到的数据符号输入到所述MAC块; 向该位置写入中间结果，使用所选择的至少一对N个接收到的数据符号产生的MAC块; 并输出N个二进制符号。

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