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    MEMORY DEVICE AND OPERATING METHOD THEREOF
    11.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220270661A1

    公开(公告)日：2022-08-25

    申请号：US17408454

    申请日：2021-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

    Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when t the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL
    12.
    发明申请
    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL 有权

    公开(公告)号：US20210384919A1

    公开(公告)日：2021-12-09

    申请号：US17199803

    申请日：2021-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunae Lee ,  Kijun Lee ,  Yeonggeol Song ,  Myungkyu Lee ,  Seokha Hwang

    IPC: H03M13/15 ,  G06F11/10

    Abstract: An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    16.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240233798A9

    公开(公告)日：2024-07-11

    申请号：US18327335

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

    Wireless network device
    17.
    外观设计
    Wireless network device 有权

    公开(公告)号：USD1034560S1

    公开(公告)日：2024-07-09

    申请号：US29854340

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Designer： Eunae Lee

    Abstract: FIG. 1 is a front perspective view of a wireless network device, showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a rear perspective thereof.
    The broken lines in the figures depict portions of a wireless network device that form no part of the claimed design.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    18.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240135980A1

    公开(公告)日：2024-04-25

    申请号：US18327335

    申请日：2023-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

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