公开(公告)号：US20240339453A1

公开(公告)日：2024-10-10

申请号：US18544670

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Donghoon Hwang ,  Inchan Hwang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional (3D) semiconductor device includes a substrate including a first surface and a second surface that are opposite to each other, a lower active region on the first surface of the substrate, the lower active region including a lower channel pattern and a lower source/drain pattern that are electrically connected to each other, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source/drain pattern that are electrically connected to each other, a dam pattern that vertically extends from the lower source/drain pattern to the upper source/drain pattern, a lower active contact electrically connected to the lower source/drain pattern, an upper active contact electrically connected to the upper source/drain pattern, and a vertical via that vertically extends along the dam pattern to electrically connect the lower active contact to the upper active contact.

公开(公告)号：US12034043B2

公开(公告)日：2024-07-09

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

公开(公告)号：US20240170554A1

公开(公告)日：2024-05-23

申请号：US18511553

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwoo Kim ,  Sungmin Kim ,  Yongjun Nam ,  Ingeon Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in a first direction on a substrate; channel layers arranged on the active pattern; a gate structure crossing the active pattern, and surrounding the plurality of channel layers, the gate structure extending in a second direction that crosses the first direction; and source/drain regions provided on the active pattern on both sides of the gate structure, and including a first epitaxial layer connected to each of side surfaces of the channel layers, and a second epitaxial layer provided on the first epitaxial layer and having a composition different from that of the first epitaxial layer. Each of the side surfaces of the plurality of channel layers has a crystal plane of (111) or (100). The first epitaxial layer extends in the second direction and has a first thickness in the first direction that is substantially constant.

公开(公告)号：US11961839B2

公开(公告)日：2024-04-16

申请号：US18133156

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jihye Lee ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/161 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L29/161

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

公开(公告)号：US20230051602A1

公开(公告)日：2023-02-16

申请号：US17725180

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Hyojin Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwon Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

公开(公告)号：US11171135B2

公开(公告)日：2021-11-09

申请号：US16896423

申请日：2020-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jihye Lee ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/161

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

公开(公告)号：US09588678B2

公开(公告)日：2017-03-07

申请号：US14474016

申请日：2014-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Inhyung Jung

IPC: G06F3/041 ,  G06F3/0488 ,  G06K9/00

CPC classification number: G06F3/04883 ,  G06K9/00416

Abstract: A method of operating electronic handwriting includes receiving at least two handwriting strokes from a touch screen, determining whether the at least two handwriting strokes overlap each other, selecting at least one of the overlapped handwriting strokes into a group, and recognizing a handwriting stroke belonging to the group. An electronic device for recognizing handwriting includes at least one of a touch device configured to receive a handwriting strokes, a storage configured to store information comprising the at least one handwriting stroke, and a controller configured to determine whether at least two handwriting strokes overlap each other, select at least one of the overlapped handwriting strokes into a group, and perform text recognition on a handwriting strokes belonging to the group.

Abstract translation: 操作电子手写的方法包括从触摸屏接收至少两个手写笔划，确定所述至少两个手写笔划是否彼此重叠，将重叠的手写笔画中的至少一个选择为一组，以及识别属于 群组。 用于识别笔迹的电子设备包括被配置为接收手写笔划的触摸设备中的至少一个，被配置为存储包括至少一个笔迹笔划的信息的存储器以及被配置为确定至少两个手写笔划是否彼此重叠的控制器 将重叠的手写笔画中的至少一个选择为组，并对属于该组的笔迹笔划执行文本识别。

公开(公告)号：US20240322039A1

公开(公告)日：2024-09-26

申请号：US18421001

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Ingeon Hwang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392

Abstract: The integrated circuit device includes a fin-type active region extending in a first direction, a channel region on the fin-type active region, a gate line on the channel region and extending in a second direction, and a source/drain region on the fin-type active region and in contact with the channel region, wherein the source/drain region includes a plurality of semiconductor layers including a first semiconductor layer that includes a portion in contact with the channel region and a portion in contact with the fin-type active region, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, a germanium (Ge) content ratio in the first semiconductor layer is greater than or equal to 10 at % and less than 100 at %, and the Ge content ratio in the first semiconductor layer decreases towards a boundary with the second semiconductor layer.

公开(公告)号：US20240321885A1

公开(公告)日：2024-09-26

申请号：US18476688

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Ingyu Jang ,  Sujin Jung ,  Gyeom Kim ,  Hyojin Kim ,  Yongjun Nam ,  Sangmoon Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823871

Abstract: An integrated circuit device includes a first transistor comprising a first conductivity type, which includes a first channel region and a first source/drain region, a second transistor comprising a second conductivity type, which includes a second channel region and a second source/drain region, a first contact structure that contacts the first source/drain region and comprising a first length, and the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance, and a second contact structure that contacts the second source/drain region and having a second length that is greater than the first length, the second contact extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance, which is greater than the first vertical distance.

公开(公告)号：US11978805B2

公开(公告)日：2024-05-07

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/66484 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.