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公开(公告)号：US12040751B2
公开(公告)日：2024-07-16
申请号：US18131429
申请日：2023-04-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam
CPC classification number: H03F1/301 , G09G3/20 , H03F3/45264 , H04R3/02 , G09G2310/0291 , H03F2200/447 , H04R2499/11 , H04R2499/13 , H04R2499/15
Abstract: An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.
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公开(公告)号：US20210172999A1
公开(公告)日：2021-06-10
申请号：US16925389
申请日：2020-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam , Sangyoung Lee
IPC: G01R31/28 , G01R31/3167
Abstract: A test circuit for testing a monitoring circuit includes: a ramp generator configured to generate a ramp signal in response to an activated first control signal; a counter configured to count pulses of a clock signal in response to the activated first control signal; at least one register configured to store an output value of the counter based on a change in at least one output signal generated by the monitoring circuit in response to the ramp signal in a test mode; and a controller configured to generate the first control signal and verify the monitoring circuit based on a ratio of a value stored in the at least one register to a duration during which the first control signal is activated.
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公开(公告)号：US12040799B2
公开(公告)日：2024-07-16
申请号：US18154966
申请日：2023-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Nam , Jaehyuk Yang , Yongsung Cho
Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuit configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.
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14.发明公开公开(公告)号：US20240036626A1
公开(公告)日：2024-02-01
申请号：US18137665
申请日：2023-04-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam , Seongmun Park , Yongsung Cho
IPC: G06F1/3203
CPC classification number: G06F1/3203
Abstract: An operating method of a power management integrated circuit includes outputting a first enable signal of a first regulator at a high level, determining whether a detection signal of a second regulator has a high level when a second enable signal of the second regulator has a low level, changing set values of the first regulator and the second regulator for a parallel mode when the detection signal has a high level, setting the first regulator and the second regulator to the changed set values, and outputting the second enable signal at a high level.
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公开(公告)号：US11824545B2
公开(公告)日：2023-11-21
申请号：US17831559
申请日：2022-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Nam
CPC classification number: H03K5/1565 , H02M3/00 , H03K3/017 , H03K4/08
Abstract: A duty point detection circuit receiving an input signal and generating an output signal includes a charge pump receiving the input signal and the output signal and generating a comparison target signal from the input signal and the output signal, a magnitude of the comparison target signal being determined based on a first duty ratio of the input signal and a second duty ratio of the output signal, a comparator receiving a reference signal and the comparison target signal, and comparing the reference signal and the comparison target signal to generate a comparison result signal, and a control circuit receiving the input signal and the comparison result signal and adjusting the second duty ratio of the output signal to a constant duty ratio in successive cycle periods of the input signal.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11486913B2
公开(公告)日：2022-11-01
申请号：US17007446
申请日：2020-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam
IPC: G01R19/165 , G06F1/28 , H03K17/687 , H03K19/21
Abstract: An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.
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公开(公告)号：US11460873B2
公开(公告)日：2022-10-04
申请号：US17338336
申请日：2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam , Jeongwoon Kong , Junhyun Bae , Sangyoung Lee
IPC: G05F1/56
Abstract: A power management integrated circuit (PMIC) includes; a DC-DC converter configured to provide output power to a load, a controller configured to control switching of the DC-DC converter, and a sense circuit including a capacitive element and configured to detect an output current flowing through a node between the DC-DC converter and the load.
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公开(公告)号：US11323110B2
公开(公告)日：2022-05-03
申请号：US17079579
申请日：2020-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam
Abstract: A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.
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公开(公告)号：US11637533B2
公开(公告)日：2023-04-25
申请号：US17240630
申请日：2021-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunseok Nam
Abstract: An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.
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公开(公告)号：US20220393674A1
公开(公告)日：2022-12-08
申请号：US17831559
申请日：2022-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Nam
Abstract: A duty point detection circuit receiving an input signal and generating an output signal includes a charge pump receiving the input signal and the output signal and generating a comparison target signal from the input signal and the output signal, a magnitude of the comparison target signal being determined based on a first duty ratio of the input signal and a second duty ratio of the output signal, a comparator receiving a reference signal and the comparison target signal, and comparing the reference signal and the comparison target signal to generate a comparison result signal, and a control circuit receiving the input signal and the comparison result signal and adjusting the second duty ratio of the output signal to a constant duty ratio in successive cycle periods of the input signal.
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