公开(公告)号：US20140051246A1

公开(公告)日：2014-02-20

申请号：US13962479

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chae Lyoung Kim ,  Ilyoung Yoon ,  Boun Yoon

IPC: H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include preparing a semiconductor substrate, forming insulating patterns including a trench on the semiconductor substrate, conformally forming a metal layer covering an inner surface of the trench on the insulating patterns, conformally forming a protecting layer on the metal layer, and performing a chemical mechanical polishing (CMP) process on the protecting layer and the metal layer until top surfaces of the insulating patterns are exposed, thereby forming a metal pattern and a protecting pattern in the trench. The CMP process may use a slurry including polishing particles having negative charges.

Abstract translation: 提供制造半导体器件的方法。 所述方法可以包括制备半导体衬底，在半导体衬底上形成包括沟槽的绝缘图案，保形地形成覆盖绝缘图案上的沟槽的内表面的金属层，在金属层上保形地形成保护层，并执行 在保护层和金属层上的化学机械抛光（CMP）工艺直到绝缘图案的顶表面露出，从而在沟槽中形成金属图案和保护图案。 CMP工艺可以使用包含具有负电荷的抛光颗粒的浆料。

公开(公告)号：US12207457B2

公开(公告)日：2025-01-21

申请号：US18413434

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US11765880B2

公开(公告)日：2023-09-19

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H10B12/00

CPC classification number: H10B12/01

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

公开(公告)号：US20230030176A1

公开(公告)日：2023-02-02

申请号：US17662316

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Jinwoo Bae ,  Boun Yoon ,  Ilyoung Yoon

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

公开(公告)号：US20220344345A1

公开(公告)日：2022-10-27

申请号：US17859247

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US20220115379A1

公开(公告)日：2022-04-14

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

公开(公告)号：US10535533B2

公开(公告)日：2020-01-14

申请号：US15868544

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Choongseob Shin ,  Hyojin Oh ,  Boun Yoon ,  Ilyoung Yoon

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/768 ,  H01L25/065 ,  H01L49/02 ,  H01L21/48

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.