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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250024666A1

    公开(公告)日：2025-01-16

    申请号：US18740166

    申请日：2024-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yanghee Lee ,  Hyukmin Kim ,  Donghoon Kwon ,  Jonghyuk Park

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a substrate including a memory cell region in which active regions are defined, a peripheral region in which a logic active region is defined, and a boundary region including a region isolation trench between the memory cell region and the peripheral region, a boundary structure including a boundary isolation layer, a region isolation structure, and a region isolation filling layer sequentially disposed in the region isolation trench, and a word line extending across the active regions, wherein among the active regions, an active region located at an outermost part of the memory cell region and the region isolation structure are spaced apart from each other by a first width, and the word line extends by an extension length less than the first width from an edge of the active region located at the outermost part of the memory cell region towards the region isolation structure.

    Semiconductor devices and methods of manufacturing the same
    2.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11411004B2

    公开(公告)日：2022-08-09

    申请号：US16903040

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H01L27/108

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    Method of fabricating semiconductor device
    3.
    发明授权
    Method of fabricating semiconductor device 有权

    公开(公告)号：US10756092B2

    公开(公告)日：2020-08-25

    申请号：US16814387

    申请日：2020-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

    IPC: H01L27/108 ,  H01L21/66

    Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240422966A1

    公开(公告)日：2024-12-19

    申请号：US18736748

    申请日：2024-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Hyesung Park ,  Seungji Kang ,  Seongeun Kim ,  Dongwon Lee ,  Juyeon Han

    IPC: H10B12/00 ,  H01L23/528

    Abstract: An integrated circuit device includes a substrate having a memory cell area and a peripheral circuit area extending around the memory cell area, cell transistors in the memory cell area, and a peripheral circuit transistor in the peripheral circuit area. The device further includes: a capacitor structure including lower electrodes on the cell transistors, a dielectric layer on a surface of the lower electrodes, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer on the metal plate layer in the memory cell area and on the peripheral circuit transistor in the peripheral circuit area; and an etch stop pattern in the interlayer insulating layer at a boundary portion of the memory cell area and the peripheral circuit area. The etch stop pattern is spaced laterally from a sidewall of the metal plate layer and extends vertically.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240155830A1

    公开(公告)日：2024-05-09

    申请号：US18413434

    申请日：2024-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    Semiconductor devices and methods of manufacturing the same
    10.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11910594B2

    公开(公告)日：2024-02-20

    申请号：US17859247

    申请日：2022-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

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