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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240341086A1

    公开(公告)日：2024-10-10

    申请号：US18622473

    申请日：2024-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/50

    Abstract: An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240155830A1

    公开(公告)日：2024-05-09

    申请号：US18413434

    申请日：2024-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    Semiconductor devices and methods of manufacturing the same
    5.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11910594B2

    公开(公告)日：2024-02-20

    申请号：US17859247

    申请日：2022-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210134806A1

    公开(公告)日：2021-05-06

    申请号：US16903040

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H01L27/108

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240422966A1

    公开(公告)日：2024-12-19

    申请号：US18736748

    申请日：2024-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Hyesung Park ,  Seungji Kang ,  Seongeun Kim ,  Dongwon Lee ,  Juyeon Han

    IPC: H10B12/00 ,  H01L23/528

    Abstract: An integrated circuit device includes a substrate having a memory cell area and a peripheral circuit area extending around the memory cell area, cell transistors in the memory cell area, and a peripheral circuit transistor in the peripheral circuit area. The device further includes: a capacitor structure including lower electrodes on the cell transistors, a dielectric layer on a surface of the lower electrodes, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer on the metal plate layer in the memory cell area and on the peripheral circuit transistor in the peripheral circuit area; and an etch stop pattern in the interlayer insulating layer at a boundary portion of the memory cell area and the peripheral circuit area. The etch stop pattern is spaced laterally from a sidewall of the metal plate layer and extends vertically.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    8.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240324172A1

    公开(公告)日：2024-09-26

    申请号：US18612672

    申请日：2024-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Yanghee Lee

    IPC: H10B12/00

    CPC classification number: H10B12/09 ,  H10B12/0335

    Abstract: A method of manufacturing a semiconductor device includes preparing a substrate including a plurality of active regions and a peripheral active region defined by an isolation layer, forming a word line in a word line trench that crosses the plurality of active regions, forming a plurality of bit line structures, each of the plurality of bit line structures including a bit line on the plurality of active regions, forming a plurality of gate line structures, each of the plurality of gate line structures including a gate line on the peripheral active region, forming a plurality of buried contacts between the plurality of bit line structures, the plurality of buried contacts being connected to the plurality of active regions, and forming an inter-gate insulating layer between the plurality of gate line structures, the inter-gate insulating layer including an oxide having impurities.

    Electronic device and method for controlling reset of control IC
    9.
    发明授权
    Electronic device and method for controlling reset of control IC 有权

    公开(公告)号：US11249559B2

    公开(公告)日：2022-02-15

    申请号：US17004147

    申请日：2020-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeongsoon Park ,  Dongil Son ,  Jeonggyu Jo ,  Yanghee Lee

    IPC: G06F3/023 ,  G06F1/28 ,  G06F3/041 ,  G06F11/07

    Abstract: Certain embodiments of the disclosure relate to an electronic device and a method for controlling a reset of a control IC. The electronic device may include a battery, at least one sensor, a control IC operatively connected to the at least one sensor, a reset IC operatively connected to the control IC, and a power supply unit operatively connected to the reset IC, wherein when an operation signal is not received from the control IC for a predetermined time, the reset IC is configured to control a voltage and/or current being applied to the control IC by controlling the power supply unit. Other certain embodiments are possible.

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