公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US20210357279A1

公开(公告)日：2021-11-18

申请号：US17198979

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoung Lee ,  Dongyoon Kim ,  Minhyouk Kim ,  Jihyuk Oh ,  Insu Choi

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/1036 ,  G06F9/455

Abstract: A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

公开(公告)号：US10990463B2

公开(公告)日：2021-04-27

申请号：US16218720

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Jiseok Kang ,  Minsoo Kim ,  Byungjik Kim ,  Wonjae Shin ,  Donghoon Lee ,  Yeonhwa Lee ,  Ho-Young Lee ,  Youjin Jang ,  Insu Choi

IPC: G06F11/07 ,  G06F12/02 ,  G06F12/0804 ,  G06F11/14

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

公开(公告)号：US20190310784A1

公开(公告)日：2019-10-10

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

公开(公告)号：US20190310783A1

公开(公告)日：2019-10-10

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US11721408B2

公开(公告)日：2023-08-08

申请号：US17388238

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daejeong Kim ,  Namhyung Kim ,  Dohan Kim ,  Deokho Seo ,  Wonjae Shin ,  Insu Choi

IPC: G01R31/28 ,  G11C29/42 ,  G11C29/50 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/5004

Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US11481149B2

公开(公告)日：2022-10-25

申请号：US16706078

申请日：2019-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young Lim ,  Ki-Seok Oh ,  Sungyong Seo ,  Youngjin Cho ,  Insu Choi

IPC: G06F3/06 ,  G11C14/00 ,  G11C11/406

Abstract: A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.

公开(公告)号：US11474717B2

公开(公告)日：2022-10-18

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.