公开(公告)号：US20210184010A1

公开(公告)日：2021-06-17

申请号：US17016877

申请日：2020-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soogine CHONG ,  Jongseob KIM ,  Joonyong KIM ,  Younghwan PARK ,  Junhyuk PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L29/423 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/02 ,  H01L21/285 ,  H01L21/765 ,  H01L29/66

Abstract: A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

公开(公告)号：US20240274689A1

公开(公告)日：2024-08-15

申请号：US18436512

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Boram KIM ,  Sunkyu HWANG

IPC: H01L29/47 ,  H01L27/095 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/7786

Abstract: A HEMT may include a channel layer including a 2DEG as a channel carrier, first and second electrodes separated on the channel layer, a first semiconductor layer on the channel layer between the first and second electrodes and having a greater band gap greater than the channel layer, a gate stack on the first semiconductor layer, and a gate electrode in ohmic contact with the gate stack. The gate stack may include a lower layer contacting the first semiconductor layer, a second semiconductor layer providing a Schottky barrier on the lower layer, and an upper layer on the second semiconductor layer. The upper layer may be doped with a p-type dopant and may have a lower band gap than the second semiconductor layer.

公开(公告)号：US20240096944A1

公开(公告)日：2024-03-21

申请号：US18133276

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG

IPC: H01L29/06 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66 ,  H10N39/00

CPC classification number: H01L29/0657 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66462 ,  H10N39/00 ,  H01L29/7786

Abstract: Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

公开(公告)号：US20220416071A1

公开(公告)日：2022-12-29

申请号：US17902383

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

公开(公告)号：US20220148947A1

公开(公告)日：2022-05-12

申请号：US17192439

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor device package includes a lead frame, a semiconductor device including a first face connected to the lead frame, a second face that faces the first face, a gate pad, a drain pad, and a source pad, the gate pad exposed on the second face of the semiconductor, the drain pad exposed on the second face of the second face, and the source pad exposed on the second face, a gate clip connected to the gate pad, a drain clip connected to the drain pad, a source clip connected to the source pad, the source clip connected to the lead frame, and a molding that seals the lead frame, the semiconductor device, the source clip, the drain clip, and the gate clip.

公开(公告)号：US20210399120A1

公开(公告)日：2021-12-23

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Joonyong KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Boram KIM ,  Younghwan PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/66

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US20210305418A1

公开(公告)日：2021-09-30

申请号：US16939274

申请日：2020-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66

Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

公开(公告)号：US20210118814A1

公开(公告)日：2021-04-22

申请号：US16868745

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/15

Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

公开(公告)号：US20240258398A1

公开(公告)日：2024-08-01

申请号：US18381945

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a p-type gallium nitride (GaN) layer on the barrier layer, an n-type interfacial layer on the p-type GaN layer, and a gate electrode on the n-type interfacial layer.

公开(公告)号：US20240243177A1

公开(公告)日：2024-07-18

申请号：US18347223

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong KIM ,  Jaejoon OH ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of manufacturing a semiconductor device according to various example embodiments includes forming a buffer layer and a first semiconductor layer on a substrate, forming a recess by etching the first semiconductor layer, sequentially forming a second semiconductor layer and a third semiconductor layer on the first semiconductor layer in which the recess is formed, and forming a source and a drain respectively in contact with both sides of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.