公开(公告)号：US10373961B2

公开(公告)日：2019-08-06

申请号：US15884504

申请日：2018-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic Yoon ,  Ki-seok Lee ,  Jung-hyun Kim ,  Je-min Park

IPC: H01L29/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.

公开(公告)号：US09391202B2

公开(公告)日：2016-07-12

申请号：US14284952

申请日：2014-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/785

Abstract: The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.

Abstract translation: 该半导体器件包括：在第一方向上延伸的半导体层，该半导体层包括一对源极/漏极区域和沟道区域，在半导体层上延伸以覆盖沟道区域的栅极以及介于 所述沟道区域和所述栅极，具有第一表面和第二表面的角部绝缘间隔物，所述第一表面沿着所述栅极的侧壁在所述第二方向延伸，所述第一表面从所述栅极介电层的侧部覆盖到 栅极的侧壁的至少一部分和覆盖半导体层的一部分的第二表面，以及覆盖在角绝缘垫片上方的栅极侧壁的外部绝缘垫片，外部绝缘垫片具有 可以提供比角绝缘间隔物更小的介电常数。

公开(公告)号：US20140327056A1

公开(公告)日：2014-11-06

申请号：US14261822

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Park ,  Je-min Park ,  Tai-heui Cho

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28044 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4925

Abstract: A semiconductor device having a contact plug is manufactured. The semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a gate electrode on the substrate, and an interlayer dielectric layer on the substrate. The interlayer dielectric layer has an upper surface having a first height.The device further comprises a contact hole extending through the interlayer dielectric layer and a contact plug having an upper surface and electrically connecting to the substrate in the contact hole. The upper surface of the contact plug has a second height lower than the first height. A spacer is on the sidewall of the contact hole. A first conductive line is on the spacer and the upper surface of the contact plug.

Abstract translation: 制造具有接触插头的半导体器件。 半导体器件包括具有单元阵列区域和外围电路区域的衬底，衬底上的栅极电极和衬底上的层间电介质层。 层间介电层具有第一高度的上表面。 该装置还包括延伸穿过层间电介质层的接触孔和具有上表面并在接触孔中电连接到基底的接触插塞。 接触塞的上表面具有比第一高度低的第二高度。 间隔件位于接触孔的侧壁上。 第一导线位于间隔件和接触插塞的上表面上。

公开(公告)号：US10541302B2

公开(公告)日：2020-01-21

申请号：US15881863

申请日：2018-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/108 ,  G11C11/408

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US10128252B2

公开(公告)日：2018-11-13

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Lee ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

公开(公告)号：US20180175045A1

公开(公告)日：2018-06-21

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok LEE ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408

CPC classification number: H01L27/10897 ,  G11C11/4085 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42376

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

公开(公告)号：US09755050B2

公开(公告)日：2017-09-05

申请号：US15174392

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Park

IPC: H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/785

Abstract: The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.

公开(公告)号：US09576902B2

公开(公告)日：2017-02-21

申请号：US15240156

申请日：2016-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-min Park ,  Yoo-sang Hwang

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L24/02 ,  H01L24/08 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/15313

Abstract: A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

Abstract translation: 半导体器件包括与衬底间隔开的导线，以及在导线之间的绝缘间隔结构，并限定接触孔。 绝缘间隔物结构邻近至少一条导电线的侧壁。 该装置还包括导电线上的绝缘图案和绝缘间隔结构，以及限定连接到接触孔的着陆焊盘孔的另一绝缘图案。 接触插塞形成在接触孔中并且连接到有源区域。 着陆垫形成在着陆垫孔中并连接到接触塞。 着陆垫垂直地重叠一对导线结构之一。