公开(公告)号：US20140327056A1

公开(公告)日：2014-11-06

申请号：US14261822

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Park ,  Je-min Park ,  Tai-heui Cho

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28044 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4925

Abstract: A semiconductor device having a contact plug is manufactured. The semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a gate electrode on the substrate, and an interlayer dielectric layer on the substrate. The interlayer dielectric layer has an upper surface having a first height.The device further comprises a contact hole extending through the interlayer dielectric layer and a contact plug having an upper surface and electrically connecting to the substrate in the contact hole. The upper surface of the contact plug has a second height lower than the first height. A spacer is on the sidewall of the contact hole. A first conductive line is on the spacer and the upper surface of the contact plug.

Abstract translation: 制造具有接触插头的半导体器件。 半导体器件包括具有单元阵列区域和外围电路区域的衬底，衬底上的栅极电极和衬底上的层间电介质层。 层间介电层具有第一高度的上表面。 该装置还包括延伸穿过层间电介质层的接触孔和具有上表面并在接触孔中电连接到基底的接触插塞。 接触塞的上表面具有比第一高度低的第二高度。 间隔件位于接触孔的侧壁上。 第一导线位于间隔件和接触插塞的上表面上。

公开(公告)号：US10686122B2

公开(公告)日：2020-06-16

申请号：US15983255

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Park ,  Ju-hyun Kim ,  Se-chung Oh ,  Dong-kyu Lee ,  Jung-min Lee ,  Kyung-il Hong

IPC: H01L43/02 ,  H01L43/12 ,  H01L23/532 ,  H01L27/22 ,  H01L23/538 ,  H01L45/00 ,  H01L27/24 ,  G11C11/16 ,  G11C13/00

Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.

公开(公告)号：US20190324854A1

公开(公告)日：2019-10-24

申请号：US16389080

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-hwan Park ,  Tae-young Oh ,  Hyung-joon Chi ,  Kyung-soo Ha ,  Hyong-ryol Hwang

IPC: G06F11/10 ,  G11C7/22

Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.