公开(公告)号：US20180190718A1

公开(公告)日：2018-07-05

申请号：US15906550

申请日：2018-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/102

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.