公开(公告)号：US09741764B1

公开(公告)日：2017-08-22

申请号：US15257609

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki Terai ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/00 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/10 ,  G11C13/00 ,  H01L27/06

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

公开(公告)号：US11183538B2

公开(公告)日：2021-11-23

申请号：US16835667

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US20180190718A1

公开(公告)日：2018-07-05

申请号：US15906550

申请日：2018-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/102

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US11201192B2

公开(公告)日：2021-12-14

申请号：US17030425

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US10062841B2

公开(公告)日：2018-08-28

申请号：US15362906

申请日：2016-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-mok Park ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

公开(公告)号：US09941333B2

公开(公告)日：2018-04-10

申请号：US15288233

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/082 ,  H01L27/24 ,  H01L29/12 ,  H01L45/00 ,  H01L27/102 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US10580979B2

公开(公告)日：2020-03-03

申请号：US16109914

申请日：2018-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-mok Park ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

公开(公告)号：US10263040B2

公开(公告)日：2019-04-16

申请号：US15906550

申请日：2018-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  H01L21/20 ,  G11C13/00

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US09991315B2

公开(公告)日：2018-06-05

申请号：US15632969

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki Terai ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/00 ,  H01L27/24 ,  H01L45/00 ,  H01L27/06 ,  G11C13/00 ,  H01L27/10 ,  H01L27/11582 ,  H01L43/08

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.