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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20230124660A1

    公开(公告)日：2023-04-20

    申请号：US17938651

    申请日：2022-10-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinhoon Jang ,  Kyungryun Kim

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array and a plurality of data input/output (I/O) pins. The plurality of data I/O pins is configured to receive write data to be stored in the memory cell array or to output read data stored in the memory cell array. The semiconductor memory device is configured to perform a burst operation in which a single data set comprising a plurality of data bits is input or output through the plurality of data I/O pins based on a single command received from an external memory controller. A number of the plurality of data I/O pins corresponds to an integer that is not a power-of-two. A burst length representing a unit of the burst operation corresponds to an integer that is not a power-of-two.

    Semiconductor memory devices
    12.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US12066893B2

    公开(公告)日：2024-08-20

    申请号：US18226622

    申请日：2023-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28

    CPC classification number: G06F11/1068

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    Semiconductor memory devices
    15.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11762736B2

    公开(公告)日：2023-09-19

    申请号：US17580048

    申请日：2022-01-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10 ,  G06F11/07 ,  G06F13/28 ,  G06F13/16 ,  G06F11/30

    CPC classification number: G06F11/1068

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    SEMICONDUCTOR MEMORY DEVICES
    16.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220374309A1

    公开(公告)日：2022-11-24

    申请号：US17580048

    申请日：2022-01-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

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