公开(公告)号：US20240281402A1

公开(公告)日：2024-08-22

申请号：US18460954

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Younghyun Lee ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jinin So

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0002

Abstract: A computing system includes an interconnect device, a plurality of memory devices electrically coupled to communicate with the interconnect device, a plurality of host devices electrically coupled to communicate with the interconnect device and configured to generate requests for access to the plurality of memory devices via the interconnect device, and a plurality of congestion monitors. These congestion monitors are configured to generate congestion information by monitoring a congestion degree of signal transfers with respect to at least one of the plurality of memory devices and the interconnect device in real time. The computing system is also configured to control at least one of: a memory region allocation of the plurality of host devices to the plurality of memory devices, and a signal transfer path inside the interconnect device, based on the congestion information.

公开(公告)号：US20240248609A1

公开(公告)日：2024-07-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240201858A1

公开(公告)日：2024-06-20

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US11922068B2

公开(公告)日：2024-03-05

申请号：US17666212

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eldho Mathew Pathiyakkara Thombra ,  Ravi Shankar Venkata Jonnalagadda ,  Prashant Vishwanath Mahendrakar ,  Jinin So ,  Jong-Geon Lee ,  Vishnu Charan Thummala

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) is provided that includes random access memory (RAM), a Near-Memory-Processing (NMP) circuit and a first control port. The NMP circuit is for receiving a command from a host system, determining an operation to be performed on the RAM in response to the command, and a location of data within the RAM with respect to the determined operation. The first control port interacts with a second control port of the host system to enable the NMP circuit to exchange control information with the host system in response to the received command.

公开(公告)号：US11531618B2

公开(公告)日：2022-12-20

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4093 ,  G11C11/4096 ,  H04N21/426

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

公开(公告)号：US20210390049A1

公开(公告)日：2021-12-16

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.