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公开(公告)号:US20210066123A1
公开(公告)日:2021-03-04
申请号:US16741187
申请日:2020-01-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaewon Hwang , Jinnam Kim , Kwangjin Moon , Kunsang Park , Myungjoo Park
IPC: H01L21/768 , H01L21/306 , H01L21/02
Abstract: Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.
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公开(公告)号:US20210005533A1
公开(公告)日:2021-01-07
申请号:US16750579
申请日:2020-01-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyoukyung Cho , Daesuk Lee , Jinnam Kim , Taeseong Kim , Kwangjin Moon , Hakseung Lee
IPC: H01L23/48 , H01L23/528 , H01L23/00 , H01L25/065 , H01L23/532 , H01L21/768 , H01L21/02 , H01L21/306
Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.
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公开(公告)号:USD885696S1
公开(公告)日:2020-05-26
申请号:US29637533
申请日:2018-02-20
Applicant: Samsung Electronics Co., Ltd.
Designer: Jinnam Kim
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公开(公告)号:USD884997S1
公开(公告)日:2020-05-19
申请号:US29649446
申请日:2018-05-30
Applicant: Samsung Electronics Co., Ltd.
Designer: Jinnam Kim , Sujin Oh , Hayoung Jang , Jungah Choi
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公开(公告)号:USD858014S1
公开(公告)日:2019-08-27
申请号:US29666935
申请日:2018-10-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Jinnam Kim , Sung-Kyung Lee , Jungah Choi
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公开(公告)号:USD830019S1
公开(公告)日:2018-10-02
申请号:US29615383
申请日:2017-08-29
Applicant: Samsung Electronics Co., Ltd.
Designer: Jinnam Kim , Jungah Choi
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公开(公告)号:USD759909S1
公开(公告)日:2016-06-21
申请号:US29523950
申请日:2015-04-15
Applicant: Samsung Electronics Co., Ltd.
Designer: Kang-Doo Kim , Jinnam Kim , Sungjae Lee , Chris Bangle
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公开(公告)号:US20240038732A1
公开(公告)日:2024-02-01
申请号:US18487247
申请日:2023-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eunsuk Jung , Hyoukyung Cho , Jinnam Kim , Hyungjun Jeon , Kwangjin Moon , Hoonjoo Na , Hakseung Lee
IPC: H01L25/065 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/08 , H01L2224/08146
Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.
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公开(公告)号:US11887966B2
公开(公告)日:2024-01-30
申请号:US17376784
申请日:2021-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinnam Kim , Seokho Kim , Hoonjoo Na , Kwangjin Moon
IPC: H01L25/065 , H01L25/18 , H01L23/48 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/48 , H01L25/18 , H01L2224/05147 , H01L2224/08145 , H01L2224/16227 , H01L2224/48227 , H01L2225/06541
Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.
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公开(公告)号:USD1010956S1
公开(公告)日:2024-01-09
申请号:US29821535
申请日:2021-12-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Myunggyu Kim , Jinnam Kim , Junghoon Hwang
Abstract: FIG. 1 is a front right perspective view of a washing machine, showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is an enlarged view of the encircled portion 8 in FIG. 1;
FIG. 9 is an enlarged view of the encircled portion 9 in FIG. 1; and,
FIG. 10 is an enlarged view of the encircled portion 10 in FIG. 4.
The even-dash broken lines illustrating portions of the washing machine form no part of the claimed design. The dot-dash lines define the boundary of the claimed design and form no part thereof. The dot-dot-dash broken lines encircling enlargement portions of the washing machine form no part of the claimed design.
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