公开(公告)号：US11699613B2

公开(公告)日：2023-07-11

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/762 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02225 ,  H01L21/2253 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/42316 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/7848

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US11251313B2

公开(公告)日：2022-02-15

申请号：US16774653

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo Kang ,  Moon Seung Yang ,  Jongryeol Yoo ,  Sihyung Lee ,  Sunguk Jang ,  Eunhye Choi

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US10797165B2

公开(公告)日：2020-10-06

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US20240321983A1

公开(公告)日：2024-09-26

申请号：US18609186

申请日：2024-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device may include a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of semiconductor patterns on the fin-type active region and separated from each other in a vertical direction, a gate line on the fin-type active region, the gate line surrounding the semiconductor patterns and extending in a second direction that intersects the first direction, a source/drain region on the fin-type active region, adjacent to the gate line and connected to the semiconductor patterns, wherein the source/drain region includes a first semiconductor layer contacting the semiconductor patterns and including a semiconductor material including a first element including at least one selected from the group consisting of fluorine, oxygen, argon, and nitrogen, and an inner spacer between the source/drain region and the gate line and including an oxide including the first element or a nitride including the first element.

公开(公告)号：US11211457B2

公开(公告)日：2021-12-28

申请号：US16899819

申请日：2020-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Choi ,  Seung Mo Kang ,  Jungtaek Kim ,  Moon Seung Yang ,  Jongryeol Yoo

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

公开(公告)号：US10903108B2

公开(公告)日：2021-01-26

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.