公开(公告)号：US11616144B2

公开(公告)日：2023-03-28

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk Jang ,  Sujin Jung ,  Jinyeong Joe ,  Jeongho Yoo ,  Seung Hun Lee ,  Jongryeol Yoo

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

公开(公告)号：US20190252526A1

公开(公告)日：2019-08-15

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US11563089B2

公开(公告)日：2023-01-24

申请号：US17471244

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin Jeong ,  Jinyeong Joe ,  Seokhoon Kim ,  Jeongho Yoo ,  Seung Hun Lee ,  Sihyung Lee

IPC: H01L21/82 ,  H01L21/76 ,  H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US10903108B2

公开(公告)日：2021-01-26

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US20250015134A1

公开(公告)日：2025-01-09

申请号：US18676686

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju Moon ,  Donggwan Shin ,  Yonghee Park ,  Myunggil Kang ,  Jeongho Yoo

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes an active region that extends on the substrate in a first direction; a plurality of semiconductor layers disposed on the active region and that are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure disposed on the substrate and that crosses the active region and the plurality of semiconductor layers, surrounds each of the plurality of semiconductor layers, and extends in a second direction; a source/drain region disposed on at least one side of the gate structure and in contact with a portion of the plurality of semiconductor layers; and an epitaxial layer that is spaced apart from an uppermost semiconductor layer, is disposed below the source/drain region and between the active region and the source/drain region, and is in contact with at least a portion of the side surfaces of the lowermost semiconductor layer.

公开(公告)号：US11699613B2

公开(公告)日：2023-07-11

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/762 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02225 ,  H01L21/2253 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/42316 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/7848

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US10797165B2

公开(公告)日：2020-10-06

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US20190309415A1

公开(公告)日：2019-10-10

申请号：US16200149

申请日：2018-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonock Han ,  Wonwoong Chung ,  Keum Seok Park ,  Pankwi Park ,  Jeongho Yoo ,  Younjoung Cho ,  Byung Koo Kong ,  Mijeong Kim ,  Jin Wook Lee ,  Changeun Jang

IPC: C23C16/448 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device includes disposing a gas-storage cylinder storing monochlorosilane within a gas supply unit. The monochlorosilane is supplied from the gas-storage cylinder into a process chamber to form a silicon containing layer therein. The gas-storage cylinder includes manganese.

公开(公告)号：US20250048696A1

公开(公告)日：2025-02-06

申请号：US18609885

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI HWAN KIM ,  Unki Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and vertically spaced apart, a source/drain pattern on the active pattern, and a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, where the source/drain pattern includes a buffer layer and a main layer on the buffer layer, the main layer includes silicon that is doped with an impurity, an impurity concentration of the main layer is a first atomic fraction at a first level corresponding to the first semiconductor pattern, and the impurity concentration of the main layer is a second atomic fraction at a second level corresponding to the second semiconductor pattern.

公开(公告)号：US11145723B2

公开(公告)日：2021-10-12

申请号：US16720363

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin Jeong ,  Jinyeong Joe ,  Seokhoon Kim ,  Jeongho Yoo ,  Seung Hun Lee ,  Sihyung Lee

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.