公开(公告)号：US12087766B2

公开(公告)日：2024-09-10

申请号：US17383749

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0669 ,  H01L29/7851

Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

公开(公告)号：US20230076270A1

公开(公告)日：2023-03-09

申请号：US17720880

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Sunguk Jang ,  Bongjin Kuh ,  Kongsoo Lee ,  Sahwan Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786

Abstract: An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

公开(公告)号：US11211456B2

公开(公告)日：2021-12-28

申请号：US16751726

申请日：2020-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20200381546A1

公开(公告)日：2020-12-03

申请号：US16732864

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US11777032B2

公开(公告)日：2023-10-03

申请号：US17533499

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/42356 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US11688813B2

公开(公告)日：2023-06-27

申请号：US17584545

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo Kang ,  Moon Seung Yang ,  Jongryeol Yoo ,  Sihyung Lee ,  Sunguk Jang ,  Eunhye Choi

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/311 ,  H01L21/3247 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/7848

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US20220209013A1

公开(公告)日：2022-06-30

申请号：US17499979

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kihwan Kim ,  Sunguk Jang ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction; a plurality of channel layers on the active region; a gate structure extending in a second direction; and a source/drain region disposed on the active region, and connected to each of the plurality of channel layers, wherein the source/drain region includes a first epitaxial layer having a lower end portion and a sidewall portion extending continuously along lateral surfaces of the plurality of channel layers, the first epitaxial layer doped with a first impurity; and a second epitaxial layer on the first epitaxial layer, having a composition, different from a composition of the first epitaxial layer, and doped with a second impurity, wherein diffusivity of the first impurity in the composition of the first epitaxial layer is lower than the diffusivity that the second impurity would have in the composition of the first epitaxial layer.

公开(公告)号：US11152517B2

公开(公告)日：2021-10-19

申请号：US16734537

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kihwan Kim ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US20210143049A1

公开(公告)日：2021-05-13

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20250046619A1

公开(公告)日：2025-02-06

申请号：US18791926

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guifu Yang ,  Sunghwan Jang ,  Sanghyeon Kim ,  Jinbum Kim ,  Hanhum Park ,  Sunguk Jang

IPC: H01L21/3115 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor apparatus includes forming a target layer, a bottom mask layer including a first mask, and a photoresist pattern, on a substrate; contracting the photoresist pattern; forming a mandrill bar on the first mask layer using the photoresist pattern that had been contracted; forming a conformal spacer layer on the first mask and the mandrill bar; etching the spacer layer such that at least a portion of the first mask is free of the spacer layer; forming a sacrificial layer on the at least the portion of the first mask; forming a hard-mask bar by etching the spacer layer and the first mask; and patterning the target layer using the hard-mask bar.