公开(公告)号：US20230260926A1

公开(公告)日：2023-08-17

申请号：US18107143

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/105 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4846 ,  H01L21/563 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/92125 ,  H01L24/92

Abstract: A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.