公开(公告)号：US12288743B2

公开(公告)日：2025-04-29

申请号：US17655573

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junwoo Park ,  Seunghwan Kim ,  Jungjoo Kim ,  Yongkwan Lee ,  Dongju Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

公开(公告)号：US20230411259A1

公开(公告)日：2023-12-21

申请号：US18110994

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Junwoo Park ,  Hyunggil Baek ,  Yongkwan Lee ,  Juhyung Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L23/49822

Abstract: A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

公开(公告)号：US20210320042A1

公开(公告)日：2021-10-14

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US11101243B2

公开(公告)日：2021-08-24

申请号：US16680657

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Kyungsuk Oh ,  Hyunki Kim ,  Yongkwan Lee ,  Sangsoo Kim ,  Seungkon Mok ,  Junyoung Oh ,  Changyoung Yoo

IPC: H01L25/065 ,  H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

公开(公告)号：US20240128190A1

公开(公告)日：2024-04-18

申请号：US18486546

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghwan Kim ,  Yongkwan Lee ,  Gyuhyeong Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5283 ,  H01L21/485 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/13026

Abstract: A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.

公开(公告)号：US20230343560A1

公开(公告)日：2023-10-26

申请号：US18217043

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  C23C16/455

CPC classification number: H01J37/32449 ,  C23C16/45504 ,  C23C16/45589 ,  H01J37/32633 ,  H01J37/32357 ,  C23C16/45591 ,  C23C16/45502 ,  C23C16/4583

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US11581266B2

公开(公告)日：2023-02-14

申请号：US17212035

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan Kim ,  Kyong Hwan Koh ,  Juhyeon Oh ,  Yongkwan Lee

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

公开(公告)号：US20210242190A1

公开(公告)日：2021-08-05

申请号：US17168706

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Kyonghwan Koh ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor package includes forming a laser reactive polymer layer on a substrate; mounting a semiconductor device on the substrate; irradiating at least a portion of the laser reactive polymer layer below the semiconductor device with a laser having a wavelength capable of penetrating through the semiconductor device on the substrate to modify the laser reactive polymer layer to have a hydrophilic functional group; and forming a first encapsulation material layer between the semiconductor device and the substrate.

公开(公告)号：US20200027818A1

公开(公告)日：2020-01-23

申请号：US16285480

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Kim ,  Sangsoo Kim ,  Seung Hwan Kim ,  Kyung Suk Oh ,  Yongkwan Lee ,  Jongho Lee

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

公开(公告)号：US20250014963A1

公开(公告)日：2025-01-09

申请号：US18763599

申请日：2024-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Kundae Yeom ,  Hyeon Hwang

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a heat-dissipating structure on the first semiconductor chip, an adhesive layer between the first semiconductor chip and the heat-dissipating structure, a second semiconductor chip on the heat-dissipating structure, a molding film on the substrate and covering at least portions of the first semiconductor chip, the heat-dissipating structure, and the second semiconductor chip, and a shield layer on an upper surface and sidewalls of the molding film, wherein the shield layer includes a first portion extending into a first hole and contacting an upper surface of the first semiconductor chip, and the first hole may penetrate the molding film, the heat-dissipating structure, and the adhesive layer.