公开(公告)号：US20240128190A1

公开(公告)日：2024-04-18

申请号：US18486546

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghwan Kim ,  Yongkwan Lee ,  Gyuhyeong Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5283 ,  H01L21/485 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/13026

Abstract: A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.

公开(公告)号：US12288743B2

公开(公告)日：2025-04-29

申请号：US17655573

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junwoo Park ,  Seunghwan Kim ,  Jungjoo Kim ,  Yongkwan Lee ,  Dongju Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

公开(公告)号：US20210320042A1

公开(公告)日：2021-10-14

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US12205925B2

公开(公告)日：2025-01-21

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20230378094A1

公开(公告)日：2023-11-23

申请号：US18104650

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Park ,  Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5385 ,  H01L23/49811 ,  H01L23/3128 ,  H10B80/00 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.

公开(公告)号：US20230260926A1

公开(公告)日：2023-08-17

申请号：US18107143

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/105 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4846 ,  H01L21/563 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/92125 ,  H01L24/92

Abstract: A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

公开(公告)号：US11688656B2

公开(公告)日：2023-06-27

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20230131730A1

公开(公告)日：2023-04-27

申请号：US17862586

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Park ,  Sangsoo Kim ,  Seunghwan Kim ,  Jungjoo Kim ,  Yongkwan Lee

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/64

Abstract: A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

公开(公告)号：US20220367416A1

公开(公告)日：2022-11-17

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US12087650B2

公开(公告)日：2024-09-10

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.