公开(公告)号：US12237297B2

公开(公告)日：2025-02-25

申请号：US18127513

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junga Lee ,  Youngja Kim ,  Hyunki Kim ,  Youngmin Lee

IPC: B23K3/00 ,  B23K1/00 ,  B23K1/015 ,  B23K3/047 ,  B23K3/08 ,  H01L23/00 ,  B23K101/40

Abstract: An apparatus includes: a vapor generating chamber configured to accommodate a heat transfer fluid and to be filled with saturated vapor generated by the heat transfer fluid; a heater configured to heat the heat transfer fluid in the vapor generating chamber; a substrate stage configured to be movable upward or downward in the vapor generating chamber and to support a substrate on which an electronic device is mounted via a solder. The apparatus also includes at least one mesh plate extending in a horizontal direction in the vapor generating chamber. The at least one mesh plate includes a plurality of openings through which the vapor moves.

公开(公告)号：US20220367416A1

公开(公告)日：2022-11-17

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20240170448A1

公开(公告)日：2024-05-23

申请号：US18470082

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Sanghyeon Jeong ,  Youngja Kim ,  Junga Lee ,  Donguk Kwon

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/3511

Abstract: A method of manufacturing a semiconductor package includes applying a plurality of forces to a plurality of points of a semiconductor chip through a plurality of elastic members, and bonding the semiconductor chip to an object while the plurality of forces are applied to the plurality of points of the semiconductor chip through the plurality of elastic members, wherein the plurality of elastic members are configured such that the plurality of forces are different from each other, and the plurality of forces flatten the semiconductor chip.

公开(公告)号：US11742294B2

公开(公告)日：2023-08-29

申请号：US17306290

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Seunghwan Kim ,  Junyoung Oh ,  Yonghyun Kim ,  Yongkwan Lee ,  Junga Lee

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

公开(公告)号：US12205925B2

公开(公告)日：2025-01-21

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20230260926A1

公开(公告)日：2023-08-17

申请号：US18107143

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/105 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4846 ,  H01L21/563 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/92125 ,  H01L24/92

Abstract: A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.