公开(公告)号：US10580488B2

公开(公告)日：2020-03-03

申请号：US16034850

申请日：2018-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chea Ouk Lim ,  Tae Hui Na ,  Jung Sunwoo ,  Yong Jun Lee

IPC: G11C13/00

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

公开(公告)号：US10409515B2

公开(公告)日：2019-09-10

申请号：US15401294

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Sunwoo ,  Makoto Hirano

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of first segments having a write data, and a plurality of second segments having a programmed information defining a programmed segment from the plurality of first segments. A randomizer is configured to randomize the write data. An error correction circuit is configured to perform an error correction operation on the write data. A control logic is configured to determine the programmed information from an address received from a memory controller, and to determine whether to operate the randomizer and the error correction circuit based on the determination of the programmed information during the program operation. A page buffer is configured to store the write data and the programmed information during the randomizing and the error correction operation.

公开(公告)号：US20190172531A1

公开(公告)日：2019-06-06

申请号：US16034850

申请日：2018-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chea Ouk Lim ,  Tae Hui Na ,  Jung Sunwoo ,  Yong Jun Lee

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2213/15 ,  G11C2213/72

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.