公开(公告)号：US20220399266A1

公开(公告)日：2022-12-15

申请号：US17837786

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongseok Song ,  Kyeongjoon Ko ,  Jaehyun Park ,  Junhan Bae ,  Jongjae Ryu ,  Nakwon Lee

IPC: H01L23/528 ,  H01L27/088

Abstract: An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

公开(公告)号：US20220149863A1

公开(公告)日：2022-05-12

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US09385730B2

公开(公告)日：2016-07-05

申请号：US14272975

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan Bae ,  Kee-won Kwon ,  Kyoungho Kim ,  Jung Hoon Chun ,  Youngsoo Sohn ,  Seok Kim

IPC: H03L7/087 ,  H03L7/081 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。