公开(公告)号：US20240085940A1

公开(公告)日：2024-03-14

申请号：US18508479

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/4291 ,  G11C7/22 ,  G11C16/32 ,  H04L7/0004 ,  H04L7/0008

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20230385209A1

公开(公告)日：2023-11-30

申请号：US18446670

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongsu KIM ,  Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

IPC: G06F13/16 ,  H04L7/00 ,  G06F1/12 ,  G06F13/40 ,  H04L1/00

CPC classification number: G06F13/1668 ,  H04L7/0008 ,  G06F1/12 ,  G06F13/4027 ,  H04L1/0002

Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.

公开(公告)号：US20230185452A1

公开(公告)日：2023-06-15

申请号：US17865621

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk RA ,  Hanbyeul NA ,  Kwanwoo NOH ,  Mankeun SEO ,  Hong Rak SON ,  Jae Hun JANG

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

公开(公告)号：US20230112284A1

公开(公告)日：2023-04-13

申请号：US18064002

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06 ,  G11C7/22 ,  G11C16/32 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.