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公开(公告)号：US10297642B2
公开(公告)日：2019-05-21
申请号：US15671735
申请日：2017-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki Terai
Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.
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公开(公告)号：US20150104921A1
公开(公告)日：2015-04-16
申请号：US14318767
申请日：2014-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Masayuki Terai , In-Gyu Baek
IPC: H01L45/00
CPC classification number: H01L45/16 , H01L27/2409 , H01L45/04 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/1675
Abstract: A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
Abstract translation: 一种制造存储器件的方法包括限定衬底上的单元区域并且在单元区域周围限定虚拟区域，在衬底的顶表面上形成位线，沿着一个方向延伸的位线，在顶部形成单元垂直结构 对应于单元区域的位线的表面，每个单元垂直结构包括单元二极管和可变电阻元件，在与虚拟区对应的位线的顶表面上形成虚拟垂直结构，每个虚拟垂直结构包括虚拟二极管 和可变电阻元件，并且形成与单元垂直结构和虚拟垂直结构的顶表面接触的字线，字线与位线成直角相交。 电池二极管包括第一杂质图案和第二杂质图案，所述虚拟二极管包括第一轻掺杂杂质图案和第二杂质图案，并且所述可变电阻元件包括第一电极，可变电阻器和第二电极。
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公开(公告)号：US20250016981A1
公开(公告)日：2025-01-09
申请号：US18653157
申请日：2024-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoonhwan Choi , Masayuki Terai
IPC: H10B12/00
Abstract: An integrated circuit memory device includes a substrate having a bit line thereon, and a channel structure extending on the bit line. The channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upwardly from one end of the horizontal portion. A word line is provided, which extends opposite the horizontal portion and crosses the bit line to extend in a second horizontal direction, which intersects the first horizontal direction. A landing pad structure is provided, and is electrically connected to the vertical channel portion. The landing pad structure includes a first contact portion in contact with an upper surface of the vertical channel portion and a second contact portion protruding downwardly from a lower surface of the first contact portion.
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公开(公告)号：US11545214B2
公开(公告)日：2023-01-03
申请号：US17361534
申请日：2021-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Masayuki Terai
Abstract: A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.
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公开(公告)号：US10910279B2
公开(公告)日：2021-02-02
申请号：US16560516
申请日：2019-09-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： You-Jin Jung , Masayuki Terai
IPC: H01L21/82 , H01L21/8239 , H01L45/00 , H01L21/8229
Abstract: A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.
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Patent Agency Ranking
公开(公告)号：US10811462B2
公开(公告)日：2020-10-20
申请号：US15188018
申请日：2016-06-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Masayuki Terai
IPC: H01L27/24 , H01L45/00 , H01L23/522
Abstract: A semiconductor device includes a first word line and a second word line extending abreast of each other in a first direction. A bit line extends between the first word line and the second word line in a second direction intersecting the first direction. A lower electrode is formed on one surface of the first word line. An ovonic threshold switch (OTS) is formed on the lower electrode. An intermediate electrode is formed on the OTS. A phase change memory (PCM) is formed on the intermediate electrode, and an upper electrode is formed between the first PCM and a surface of the bit line. The width of the first upper electrode in the second direction is narrower than the width of the first intermediate electrode in the second direction.
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公开(公告)号：US20200243764A1
公开(公告)日：2020-07-30
申请号：US16560516
申请日：2019-09-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： You-Jin JUNG , Masayuki Terai
Abstract: A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.
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公开(公告)号：US10546999B2
公开(公告)日：2020-01-28
申请号：US15346751
申请日：2016-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Masayuki Terai , Dae-Hwan Kang , Gwan-Hyeob Koh
IPC: H01L45/00
Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.
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公开(公告)号：US10522595B2
公开(公告)日：2019-12-31
申请号：US15334750
申请日：2016-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki Terai
Abstract: A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.
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公开(公告)号：US20180286919A1
公开(公告)日：2018-10-04
申请号：US15671735
申请日：2017-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki Terai
CPC classification number: H01L27/249 , H01L27/2427 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/1683
Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.
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