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公开(公告)号：US11094882B2
公开(公告)日：2021-08-17
申请号：US16360500
申请日：2019-03-21
发明人： Jung-hyun Cho , Song-yi Kim , Masayuki Terai
IPC分类号： H01L23/522 , H01L45/00 , H01L43/12
摘要： A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.
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公开(公告)号：US10825862B2
公开(公告)日：2020-11-03
申请号：US16394139
申请日：2019-04-25
发明人： Junghyun Cho , You-Jin Jung , Masayuki Terai , Jinchan Yun
摘要： A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.
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公开(公告)号：US09172039B2
公开(公告)日：2015-10-27
申请号：US14449425
申请日：2014-08-01
发明人： Masayuki Terai , In-Gyu Baek
IPC分类号： H01L21/336 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias.
摘要翻译： 提供一种制造存储器件的方法。 该方法包括在衬底上限定单元区域和驱动区域，在驱动区域上形成驱动晶体管，在单元区域中形成第一位线，设置在第一位线的上表面上的第一单元存储单元， 设置在第一单元存储单元的上表面上的字线，以及设置在字线上表面上的第二单元存储单元，形成用于填充第二单元存储单元之间并包括第二位线槽的平坦化层 第一位线的上表面，第二位线槽中的位线接触通孔，字线的端部的上表面上的浮动电极沟槽以及浮动接触通路中的每一个中的第一浮动接触通孔和第二浮动接触通孔 电极沟槽，同时在第二位线沟槽中形成第二位线，位线接触通孔中的位线接触电极，浮动电极沟槽中的浮动电极，第一f 在第一浮动接触通孔中放置接触电极，以及在第二浮动接触通孔中的第二浮动接触电极。
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公开(公告)号：US09263673B2
公开(公告)日：2016-02-16
申请号：US14609452
申请日：2015-01-30
发明人： Masayuki Terai , In-Gyu Baek
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
摘要翻译： 电阻式存储器件包括设置在下布线上的开关器件，设置在开关器件上的电阻器元件和设置在电阻器元件上的上部互连件。 开关装置包括二极管电极，设置在二极管电极上的高浓度下阳极，设置在下部高浓度阳极电极上的中等浓度下阳极，设置在中浓度下阳极上的公共阴极，低 - 设置在公共阴极上的浓缩上阳极和设置在低浓度上阳极上的高浓度上阳极。 中等浓度下阳极的峰值掺杂浓度比低浓度上阳极的峰值掺杂浓度高至少10倍。
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公开(公告)号：US10608176B2
公开(公告)日：2020-03-31
申请号：US16385052
申请日：2019-04-16
发明人： Masayuki Terai
摘要： A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.
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公开(公告)号：US09991315B2
公开(公告)日：2018-06-05
申请号：US15632969
申请日：2017-06-26
发明人： Masayuki Terai , Gwan-hyeob Koh , Dae-hwan Kang
IPC分类号： H01L27/00 , H01L27/24 , H01L45/00 , H01L27/06 , G11C13/00 , H01L27/10 , H01L27/11582 , H01L43/08
CPC分类号： H01L27/2427 , G11C11/1659 , G11C13/0002 , G11C13/003 , G11C2213/17 , G11C2213/71 , G11C2213/76 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L43/08 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
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公开(公告)号：US09118009B2
公开(公告)日：2015-08-25
申请号：US14318767
申请日：2014-06-30
发明人： Masayuki Terai , In-Gyu Baek
CPC分类号： H01L45/16 , H01L27/2409 , H01L45/04 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/1675
摘要： A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.
摘要翻译： 一种制造存储器件的方法包括限定衬底上的单元区域并且在单元区域周围限定虚拟区域，在衬底的顶表面上形成位线，沿着一个方向延伸的位线，在顶部形成单元垂直结构 对应于单元区域的位线的表面，每个单元垂直结构包括单元二极管和可变电阻元件，在与虚拟区对应的位线的顶表面上形成虚拟垂直结构，每个虚拟垂直结构包括虚拟二极管 和可变电阻元件，并且形成与单元垂直结构和虚拟垂直结构的顶表面接触的字线，字线与位线成直角相交。 电池二极管包括第一杂质图案和第二杂质图案，所述虚拟二极管包括第一轻掺杂杂质图案和第二杂质图案，并且所述可变电阻元件包括第一电极，可变电阻器和第二电极。
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公开(公告)号：US20150194603A1
公开(公告)日：2015-07-09
申请号：US14449425
申请日：2014-08-01
发明人： Masayuki Terai , In-Gyu Baek
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias.
摘要翻译： 提供一种制造存储器件的方法。 该方法包括在衬底上限定单元区域和驱动区域，在驱动区域上形成驱动晶体管，在单元区域中形成第一位线，设置在第一位线的上表面上的第一单元存储单元， 设置在第一单元存储单元的上表面上的字线，以及设置在字线上表面上的第二单元存储单元，形成用于填充第二单元存储单元之间并包括第二位线槽的平坦化层 第一位线的上表面，第二位线槽中的位线接触通孔，字线的端部的上表面上的浮动电极沟槽以及浮动接触通路中的每一个中的第一浮动接触通孔和第二浮动接触通孔 电极沟槽，同时在第二位线沟槽中形成第二位线，位线接触通孔中的位线接触电极，浮动电极沟槽中的浮动电极，第一f 在第一浮动接触通孔中放置接触电极，以及在第二浮动接触通孔中的第二浮动接触电极。
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公开(公告)号：US20200083448A1
公开(公告)日：2020-03-12
申请号：US16360500
申请日：2019-03-21
发明人： Jung-hyun Cho , Song-yi Kim , Masayuki Terai
摘要： A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.
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公开(公告)号：US10305032B2
公开(公告)日：2019-05-28
申请号：US15663065
申请日：2017-07-28
发明人： Masayuki Terai
摘要： A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.
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