公开(公告)号：US20210265251A1

公开(公告)日：2021-08-26

申请号：US17031141

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdon MUN ,  Myungsam KANG ,  Youngchan KO ,  Yieok KWON ,  Jeongseok KIM ,  Gongje LEE ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 μm or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.

公开(公告)号：US20210210414A1

公开(公告)日：2021-07-08

申请号：US17012294

申请日：2020-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Kyungdon MUN

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A semiconductor package includes a redistribution substrate having a first redistribution layer, a semiconductor chip on the redistribution substrate and connected to the first redistribution layer, a vertical connection conductor on the redistribution substrate and electrically connected to the semiconductor chip through the first redistribution layer, a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor, and an encapsulant covering at least a portion of each of the semiconductor chip, the vertical connection conductor, and the core member, the encapsulant filling the first and second through-holes, wherein the vertical connection conductor has a cross-sectional shape with a side surface tapered to have a width of a lower surface thereof is narrower than a width of an upper surface thereof, and the first and second through-holes have a cross-sectional shape tapered in a direction opposite to the vertical connection conductor.

公开(公告)号：US20240363573A1

公开(公告)日：2024-10-31

申请号：US18764827

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Myungsam KANG

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.

公开(公告)号：US20230275056A1

公开(公告)日：2023-08-31

申请号：US18141838

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Myungsam KANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/214

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.

公开(公告)号：US20230230917A1

公开(公告)日：2023-07-20

申请号：US18125529

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan Ko ,  Kyungdon MUN

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L24/14 ,  H01L23/36 ,  H01L24/20 ,  H01L24/19

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

公开(公告)号：US20230038413A1

公开(公告)日：2023-02-09

申请号：US17702440

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Jeongseok KIM ,  Bongju CHO

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first rewiring layer; a lower semiconductor chip on the first rewiring layer; an upper semiconductor chip on the lower semiconductor chip; a heat dissipation structure on the upper semiconductor chip; a molding layer on the first rewiring layer so as to contact side surfaces of the lower semiconductor chip, the upper semiconductor chip, and the heat dissipation structure; a second rewiring layer on the heat dissipation structure; and one or more connection structures on the first rewiring layer and positioned adjacent to the side surfaces of the lower semiconductor chip and the upper semiconductor chip and configured to extend through the molding layer and connect the first rewiring layer to the second rewiring layer, wherein the upper semiconductor chip and the heat dissipation structure contact each other.

公开(公告)号：US20220068784A1

公开(公告)日：2022-03-03

申请号：US17218356

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/552 ,  H01L25/10

Abstract: A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 μm, and the side shielding pattern has a width of no less than about 5 μm.

公开(公告)号：US20200176364A1

公开(公告)日：2020-06-04

申请号：US16590570

申请日：2019-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin PARK ,  Myungsam KANG ,  Younggwan KO

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

公开(公告)号：US20250029886A1

公开(公告)日：2025-01-23

申请号：US18604875

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Chilwoo KWON ,  Hyejin KIM ,  Okgyeong PARK

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18

Abstract: A semiconductor package includes: a first semiconductor chip disposed on a package substrate; a second semiconductor chip adjacent to the first semiconductor chip in a horizontal direction and disposed on the package substrate; a plurality of first thermal interfacial material patterns overlapping the first semiconductor chip in a vertical direction; a plurality of second thermal interfacial material patterns overlapping the second semiconductor chip in the vertical direction; and a first non-metal thermal conductive layer disposed between the plurality of first thermal interfacial material patterns, wherein the plurality of first thermal interfacial materials are spaced apart from the plurality of second thermal interfacial materials in the horizontal direction, and a thermal conductivity of the first non-metal thermal conductive layer in the horizontal direction is lower than a thermal conductivity of the first non-metal thermal conductive layer in the vertical direction.

公开(公告)号：US20240030145A1

公开(公告)日：2024-01-25

申请号：US18109392

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG

IPC: H01L23/538 ,  H10B80/00 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H10B80/00 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/13147 ,  H01L2224/13007 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13644 ,  H01L2224/16227 ,  H01L2924/1461 ,  H01L2924/1438 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/11825

Abstract: A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.