公开(公告)号：US20240355798A1

公开(公告)日：2024-10-24

申请号：US18500581

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Kyung Don MUN ,  Kyoung Lim SUK

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L28/10 ,  H10B80/00

Abstract: A semiconductor package including a first semiconductor structure on a first redistribution layer structure; first conductive posts on the first redistribution layer structure and next to the first side of the first semiconductor structure; second conductive posts on the first redistribution layer structure and next to a second side opposite to the first side of the first semiconductor structure; a molding material molding the first semiconductor structure, the first conductive posts, and the second conductive posts on the first redistribution layer structure; a second redistribution layer structure on the molding material; a second semiconductor structure on the second redistribution layer structure; a heat dissipation structure on the second redistribution layer structure; and a 3D solenoid inductor including some of the second conductive posts, the redistribution lines at the uppermost of the first redistribution layer structure, and the redistribution lines at the lowermost of the second redistribution layer structure.

公开(公告)号：US20220059440A1

公开(公告)日：2022-02-24

申请号：US17228784

申请日：2021-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Kyung Don MUN ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US20240145329A1

公开(公告)日：2024-05-02

申请号：US18320527

申请日：2023-05-19

Applicant: Samsung Electronics Co. Ltd.

Inventor： Geunwoo KIM ,  Kyung Don MUN

IPC: H01L23/36 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/08 ,  H01L2224/08225

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a heat dissipation layer on the first semiconductor chip and in contact with an upper surface of the first semiconductor chip, a second redistribution substrate on the heat dissipation layer, a molding layer surrounding the first semiconductor chip and the heat dissipation layer between the first redistribution substrate and the second redistribution substrate, through electrodes vertically penetrating the molding layer and electrically connecting the first redistribution substrate and the second redistribution substrate, the through electrodes being spaced apart from the first semiconductor chip and the heat dissipation layer, and dummy patterns vertically penetrating the molding layer and in contact with a side surface of the first semiconductor chip and a side surface of the heat dissipation layer. The first redistribution substrate includes a first insulating layer, first wiring patterns in the first insulating layer and electrically connecting the first semiconductor chip and the through electrodes, and second wiring patterns in the first insulating layer, electrically connected to the dummy patterns, and electrically insulated from the first wiring patterns.

公开(公告)号：US20230154836A1

公开(公告)日：2023-05-18

申请号：US18098158

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Kyung Don MUN ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/3171 ,  H01L24/16 ,  H01L23/5386 ,  H01L2224/16235

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US20230187352A1

公开(公告)日：2023-06-15

申请号：US17896241

申请日：2022-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inho ROH ,  Donghwa KWAK ,  Kyung Don MUN ,  Wonsok LEE

IPC: H01L23/528 ,  H01L27/108 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L23/5226

Abstract: A semiconductor memory device includes a substrate including active regions, the active regions having first impurity regions and second impurity regions, word lines on a first surface of the substrate, the word lines extending in a first direction, first bit lines on the word lines, the first bit lines extending in a second direction crossing the first direction, and the first bit lines being connected to the first impurity regions, first contact plugs between the first bit lines, the first contact plugs being connected to the second impurity regions, respectively, second bit lines on a second surface of the substrate, the second bit lines being electrically connected to the first impurity regions, and a first capacitor on the first contact plugs.

公开(公告)号：US20250046691A1

公开(公告)日：2025-02-06

申请号：US18544707

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Kyung Don MUN ,  Sangjin BAEK ,  Hyeonjeong HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first redistribution line structure; a first semiconductor chip on one surface of the first redistribution line structure; a first conductive bump between, and connecting, the first redistribution line structure and the first semiconductor chip; a first encapsulant encapsulating at least a portion of the first semiconductor chip; a second semiconductor chip on another, opposite surface of the first redistribution line and including a through via; a second conductive bump between, and connecting, the first redistribution line structure and the second semiconductor chip; a second encapsulant encapsulating at least a portion of the second semiconductor chip; and a second redistribution line structure on the second encapsulant. The second encapsulant covers at least a portion of a surface of the second semiconductor chip facing the second redistribution line structure.

公开(公告)号：US20240072005A1

公开(公告)日：2024-02-29

申请号：US18299896

申请日：2023-04-13

Applicant: Samsung Electronics Co, Ltd.

Inventor： Kyung Don MUN

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16221 ,  H01L2225/1094

Abstract: A semiconductor package includes a substrate, a first chip stack including a plurality of first semiconductor chips sequentially stacked on the substrate, and a second chip stack including a plurality of second semiconductor chips sequentially stacked on the first chip stack, and first and second pluralities of thermal conductive layers. The first thermal conductive layers are each between the substrate and the first chip stack, or between adjacent first semiconductor chips. The second thermal conductive layers are each between the first chip stack and the second chip stack, or between adjacent second semiconductor chips. A thermal conductivity of a second thermal interface material of the second thermal conductive layers is greater than a thermal conductivity of a first thermal interface material of the first thermal conductive layers, and a stiffness of the first thermal interface material is greater than a stiffness of the second thermal interface material.

公开(公告)号：US20230320106A1

公开(公告)日：2023-10-05

申请号：US18091832

申请日：2022-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN

IPC: H10B80/00 ,  H10B12/00

CPC classification number: H10B80/00 ,  H10B12/315

Abstract: A semiconductor package includes first and second semiconductor dies on a buffer die. The first semiconductor die includes first memory blocks on a first semiconductor substrate, a first interlayer dielectric layer, a first through via penetrating the first semiconductor substrate and connected to the buffer die, and first conductive pads on the first interlayer dielectric layer and connected to the first memory blocks. The second semiconductor die includes first calculation blocks on a second semiconductor substrate and configured to calculate data received from the first memory blocks and store results to the first memory blocks, a second interlayer dielectric layer, and second conductive pads below the second interlayer dielectric layer and connected to the first calculation blocks. A top surface of the first interlayer dielectric layer contacts the second interlayer dielectric layer. The first conductive pads contact the second conductive pads.

公开(公告)号：US20250062208A1

公开(公告)日：2025-02-20

申请号：US18623645

申请日：2024-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  Kyung Don MUN ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package may include a first redistribution layer structure, a chiplet structure on the first redistribution layer structure, a plurality of first connection members on the first redistribution layer structure, a first molding material on the first redistribution layer structure and molding the chiplet structure and the plurality of first connection members, and a second redistribution layer structure on the first molding material. The chiplet structure may include a third redistribution layer structure, a first chiplet and a second chiplet on the third redistribution layer structure, and a bridge die on a bottom surface of the third redistribution layer structure.

公开(公告)号：US20240363573A1

公开(公告)日：2024-10-31

申请号：US18764827

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Myungsam KANG

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.