公开(公告)号：US09202932B2

公开(公告)日：2015-12-01

申请号：US13834529

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Woo Paek ,  Jung-Dal Choi ,  Young-Seop Rah ,  Byung-Kwan You ,  Seok-Won Lee

IPC: H01L21/3205 ,  H01L29/792 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/764 ,  H01L27/115 ,  H01L23/522

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/11568 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.

Abstract translation: 在制造半导体器件的方法中，可以在衬底上依次形成电介质层结构和控制栅极层。 可以部分蚀刻控制栅极层以形成多个控制栅极。 栅极间隔物和牺牲隔离物可以顺序地堆叠在控制栅极的侧壁上以及电介质层结构的一部分上。 可以使用牺牲间隔物和栅极间隔物作为蚀刻掩模来部分地蚀刻电介质层结构，以形成多个电介质层结构图案。 可以去除牺牲隔离物。 可以在基板上形成绝缘中间层以形成气隙。 绝缘中间层可以覆盖电介质层结构图案，栅极间隔物和控制栅极。 气隙可以在相邻的栅极间隔件之间和相邻的介电层结构图案之间延伸。

公开(公告)号：US09099460B2

公开(公告)日：2015-08-04

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/28 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US10818728B2

公开(公告)日：2020-10-27

申请号：US15931089

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11519 ,  H01L27/06 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US20130256781A1

公开(公告)日：2013-10-03

申请号：US13834529

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Woo PAEK ,  Jung-Dal Choi ,  Young-Seop Rah ,  Byung-Kwan You ,  Seok-Won Lee

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/11568 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.

Abstract translation: 在制造半导体器件的方法中，可以在衬底上依次形成电介质层结构和控制栅极层。 可以部分蚀刻控制栅极层以形成多个控制栅极。 栅极间隔物和牺牲隔离物可以顺序地堆叠在控制栅极的侧壁上以及电介质层结构的一部分上。 可以使用牺牲间隔物和栅极间隔物作为蚀刻掩模来部分地蚀刻电介质层结构，以形成多个电介质层结构图案。 可以去除牺牲隔离物。 可以在基板上形成绝缘中间层以形成气隙。 绝缘中间层可以覆盖电介质层结构图案，栅极间隔物和控制栅极。 气隙可以在相邻的栅极间隔件之间和相邻的介电层结构图案之间延伸。