公开(公告)号：US20210384218A1

公开(公告)日：2021-12-09

申请号：US17158107

申请日：2021-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A vertical memory device includes a first gate structure on a substrate, the first gate structure including first gate electrodes spaced from each other in a first direction and stacked in a staircase shape, a second gate structure on the first gate structure and including second gate electrodes spaced from each other in the first direction and stacked in the staircase shape, a channel extending through the first and second gate structures, and a contact plug extending in the first direction through the first and second gate structures, wherein second steps at end portions of the second gate electrodes overlap first steps at end portions of the first gate electrodes, and wherein the contact plug extends through at least one of the first steps and through at least one of the second steps, while being electrically connected only to the first steps or to the second steps.

公开(公告)号：US20210242237A1

公开(公告)日：2021-08-05

申请号：US17216867

申请日：2021-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon LIM ,  SangJun HONG ,  Seokcheon BAEK

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L29/423 ,  H01L21/28

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US20230422509A1

公开(公告)日：2023-12-28

申请号：US18336497

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Seongjun SEO

IPC: H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and arranged apart from one another in a vertical direction, the gate electrodes including a ground selection line and a plurality of word lines, a pair of gate stack separation insulation layers passing through the gate electrodes and extending in a first horizontal direction in the memory cell region and the connection region, and a pad structure including a plurality of pad layers in the connection region, connected to respective ones of the gate electrodes, arranged in a staircase shape in the first horizontal direction and in a second horizontal direction, the ground selection line including a plurality of ground selection line cut regions each being apart from edges of the pad layers in the second horizontal direction.

公开(公告)号：US20230084557A1

公开(公告)日：2023-03-16

申请号：US17869909

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having cell and connection regions, and a stack structure having dielectric layers and electrodes that are vertically and alternately stacked on the substrate. The stack structure includes a first pad part, a first fence part, a second pad part, and a second fence part that are sequentially arranged along a first direction. Each of the first and second pad parts has a first stepwise structure formed along the first direction and a second stepwise structure formed along a second direction that intersects the first direction, and each of the first and second fence parts includes dummy electrodes at the same levels as the electrodes and spaced apart from the electrodes. Sidewalls of the electrodes that define second stepwise structure of the second part are offset from sidewalls of the dummy electrodes that define second dummy stepwise structure of the first pad part.

公开(公告)号：US20220392916A1

公开(公告)日：2022-12-08

申请号：US17679268

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/06

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20220157831A1

公开(公告)日：2022-05-19

申请号：US17378317

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Younghwan SON ,  Miram KWON ,  Junyong PARK ,  Jiho LEE

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer.

公开(公告)号：US20210202522A1

公开(公告)日：2021-07-01

申请号：US17198838

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/535 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region and a pad region, a first conductive line on the cell array region and the pad region of the substrate, a second conductive line between the first conductive line and the substrate, the second conductive line including a first portion on the cell array region and a second portion on the pad region and exposed by the first conductive line in a plan view, a first edge pattern between the substrate and the first conductive line and between the first and second portions of the second conductive line, and a first cell contact plug on the pad region of the substrate that penetrates the first conductive line and the first edge pattern.

公开(公告)号：US20190393241A1

公开(公告)日：2019-12-26

申请号：US16272288

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Kwang-Soo KIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528

Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.