Semiconductor device
    11.
    发明授权

    公开(公告)号:US11749678B2

    公开(公告)日:2023-09-05

    申请号:US17844807

    申请日:2022-06-21

    CPC classification number: H01L27/088 H01L29/0649 H01L29/7827

    Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

    INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME

    公开(公告)号:US20210376126A1

    公开(公告)日:2021-12-02

    申请号:US17399118

    申请日:2021-08-11

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

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