公开(公告)号：US20240063221A1

公开(公告)日：2024-02-22

申请号：US18125429

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo Lee ,  Yeonho Park ,  Minchan Gwak ,  Hojun Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66439 ,  H01L29/66545

Abstract: A semiconductor device includes active regions, gate structures intersecting the active regions and including gate electrodes, source/drain regions on the active regions on sides of the gate structures, and a gate isolation structure isolating gate structures, which oppose each other, from each other on a region between the active regions. The gate structures that oppose each other include a first gate structure, a second gate structure opposing the first gate structure, a third gate structure extending in parallel to the first gate structure, and a fourth gate structure opposing the third gate structure and extending in parallel to the second gate structure. The gate isolation structure includes a first isolation structure of a line type extending in the first horizontal direction, and second isolation structures of a hole type penetrating through the first isolation structure between the first and second gate structures and between the third and fourth gate structures.

公开(公告)号：US20240347596A1

公开(公告)日：2024-10-17

申请号：US18512322

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junmo PARK ,  Deokhwan Kim ,  Junsu Kong ,  Yeonho Park ,  Hyungjin Park ,  Sujin Lee ,  Jinseok Lee

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including a substrate having an active pattern, first and second semiconductor patterns provided on the active pattern vertically spaced apart from each other, a source/drain pattern connected to the first and second semiconductor patterns, a gate electrode between the first and second semiconductor patterns, and a gate insulating pattern enclosing the gate electrode, wherein the gate insulating pattern includes, a high-k dielectric pattern enclosing the gate electrode, an inner spacer between the high-k dielectric pattern and the source/drain pattern, and a mask insulating pattern having an etch selectivity with respect to the inner spacer between the high-k dielectric pattern and the inner spacer.

公开(公告)号：US11749678B2

公开(公告)日：2023-09-05

申请号：US17844807

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Youngchai Jung ,  Mingyu Kim ,  Seon-Bae Kim ,  Yeonho Park

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/0649 ,  H01L29/7827

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

公开(公告)号：US12266652B2

公开(公告)日：2025-04-01

申请号：US17691293

申请日：2022-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo Park ,  Yeonho Park ,  Kyubong Choi ,  Eunsil Park ,  Junseok Lee ,  Jinseok Lee

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate including a first active fin and a second active fin respectively extending in a first direction, the substrate having a recess between the first and second active fins, a device isolation film on the substrate, first and second gate structures on the first and second active fins, respectively, and extending in a second direction, and a field separation layer having a first portion between the first and second active fin and in the recess, and a second portion extending from both sides of the first portion in the second direction to an upper surface of the device isolation film. The recess has a bottom surface lower in a third direction intersecting the first direction and the second direction than the upper surface of the device isolation film, and a region of the upper surface of the device isolation film has a flat surface.

公开(公告)号：US20230005910A1

公开(公告)日：2023-01-05

申请号：US17694192

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junmo Park ,  Yeonho Park ,  Kyubong Choi ,  Cheol Kim ,  Junseok Lee ,  Jinseok Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, the gate separation pattern including a first insulating material; and a gate capping layer disposed on the first and second gate structures and having an extension portion extending between the first and second gate structures to be connected to the gate separation pattern, the gate capping layer including a second insulating material different from the first insulating material.

公开(公告)号：US20230029827A1

公开(公告)日：2023-02-02

申请号：US17685593

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo Park ,  Yeonho Park ,  Eunsil Park ,  Jinseok Lee ,  Wangseop Lim ,  Kyubong Choi

IPC: H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit semiconductor device includes a first region including first active fins extending in a first direction, and first transistors including first gate electrodes extending in a second direction, a second region in contact with the first region in the second direction, wherein the second region includes second active fins extending in the first direction, and second transistors including second gate electrodes extending in the second direction. The integrated circuit semiconductor device includes metal dams at a boundary of the first region and the second region to separate the first gate electrodes and the second gate electrodes in the second direction, wherein the metal dams, the first gate electrodes, and the second gate electrodes are electrically connected in the second direction.