公开(公告)号：US11355640B1

公开(公告)日：2022-06-07

申请号：US17167640

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A hybrid multi-stack semiconductor device and a method of manufacturing the same are provided. The hybrid multi-stack semiconductor device includes a nanosheet stack and a fin field-effect transistor (finFET) stack formed above the nanosheet stack, wherein the nanosheet stack includes a plurality of nanosheet layers formed above a substrate and enclosed by a 1st gate structure, wherein the at least one fin structure has a self-aligned form with respect to the nanosheet stack so that a left horizontal distance between a leftmost side surface of the at least one fin structure and a left side surface of the nanosheet stack is equal to a right horizontal distance between a rightmost side surface of the at least one fin structure and a right side surface of the nanosheet stack.

公开(公告)号：US12057448B2

公开(公告)日：2024-08-06

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US20230282646A1

公开(公告)日：2023-09-07

申请号：US18316005

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun Song ,  Kang-ill Seo

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L21/823878

Abstract: A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the 1st transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.

公开(公告)号：US11735585B2

公开(公告)日：2023-08-22

申请号：US17223829

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11664433B2

公开(公告)日：2023-05-30

申请号：US17366534

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Inchan Hwang

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0665

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

公开(公告)号：US12183738B2

公开(公告)日：2024-12-31

申请号：US17221355

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun Song ,  Seungyoung Lee ,  Saehan Park

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423 ,  H10B10/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

公开(公告)号：US12144163B2

公开(公告)日：2024-11-12

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US11901363B2

公开(公告)日：2024-02-13

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Myunggil Kang ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L23/535 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  G01R27/02

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US11741886B2

公开(公告)日：2023-08-29

申请号：US17712687

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Song ,  Sangtae Han ,  Huigyeong Ahn ,  Changsun Kang ,  Mijin Kim ,  Seongjun Kim ,  Changjun Park ,  Seunghee Oh ,  Kyoree Lee ,  Mihyun Lee

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0408 ,  G09G2300/0439 ,  G09G2310/0275

Abstract: A display apparatus is provided. The display apparatus includes a substrate having a data line disposed thereon, a plurality of pixel modules arranged in a matrix format on the substrate, and a driver providing a digital data signal through the data line to each of the pixel modules. Each of the pixel modules may include a light emitting layer in which a plurality of light emitting diode (LED) devices form a pixel, a driving layer comprising a display driver integrated circuit (DDI) below the light emitting layer and generating a driving signal to drive the LED devices, and a substrate layer, between the driving layer and the substrate, comprising a data input pad to receive the data signal and transmit the data signal to the DDI and a data output pad to provide the data signal to another adjacent pixel module.

公开(公告)号：US11688742B2

公开(公告)日：2023-06-27

申请号：US17335834

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673

Abstract: A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.