公开(公告)号：US20160196206A1

公开(公告)日：2016-07-07

申请号：US14909443

申请日：2014-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungik Kang ,  Jinyoung Park ,  Seungwook Lee ,  Eunseok Hong

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F12/023 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/1694 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1044 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention relates to a processor and a memory. More specifically, the present invention relates to a switchable on chip memory accessible by various master intellectual properties (IPs) and a method for controlling the same, and the method for controlling the on chip memory, according to one embodiment of the present invention, can comprise the steps of: setting memory allocation information including at least one among modes of respective master IPs, priority, space size of a required memory, and correlation with other master IPs; and allocating memories for the respective master IPs by using the memory allocation information. According to the one embodiment of the present invention, various master IPs within an embedded SoC are capable of utilizing all of the advantages of an on chip buffer and an on chip cache.

Abstract translation: 本发明涉及处理器和存储器。 更具体地，本发明涉及可通过各种主要知识产权（IP）访问的可切换片上存储器及其控制方法，并且根据本发明的一个实施例的用于控制片上存储器的方法可以 包括以下步骤：设置包括各个主IP的模式，优先级，所需存储器的空间大小以及与其他主IP的相关性中的至少一个的存储器分配信息; 以及通过使用存储器分配信息为各个主IP分配存储器。 根据本发明的一个实施例，嵌入式SoC内的各种主IP能够利用片上缓冲器和片上高速缓存的所有优点。

公开(公告)号：US12074187B2

公开(公告)日：2024-08-27

申请号：US17371424

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoun-Jee Ha ,  Seungwook Lee

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14831

Abstract: An image sensor includes a substrate having a first surface and a second surface, which are opposite to each other, the substrate including a unit pixel region including a device isolation pattern adjacent to the first surface and a photoelectric conversion region adjacent to the second surface, a pixel isolation pattern provided in the substrate to define the unit pixel regions, an impurity region in the unit pixel region and being adjacent to a side surface of the device isolation pattern, a gate electrode provided on the first surface, and an auxiliary isolation pattern provided between a first side surface of the gate electrode and the impurity region, when the image sensor is viewed in a plan view. A bottom surface of the auxiliary isolation pattern may be located at a level different from a bottom surface of the device isolation pattern.

公开(公告)号：US11967952B2

公开(公告)日：2024-04-23

申请号：US17242737

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungdal Kwon ,  Seungwook Lee ,  Youngnam Hwang

IPC: G06F30/327 ,  H03K19/1776

CPC classification number: H03K19/1776 ,  G06F30/327

Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

公开(公告)号：US10895987B2

公开(公告)日：2021-01-19

申请号：US16018790

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungik Kang ,  Jinyoung Park ,  Heesub Shin ,  Seungwook Lee

IPC: G06F3/06 ,  G06F12/02

Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

公开(公告)号：US10168934B2

公开(公告)日：2019-01-01

申请号：US14911932

申请日：2014-08-14

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Hansu Cho ,  Brent ByungHoon Kang ,  Yunheung Paek ,  Seungwook Lee ,  Junbum Shin

IPC: G06F3/06 ,  G06F12/00 ,  G06F11/30 ,  G06F13/16 ,  G06F21/79 ,  H04L29/06

Abstract: Provided is a method of memory access for a memory controller in an integrity monitoring system sharing memory with a host system. The memory access method may include: receiving a memory access command from a local processor of the integrity monitoring system; accessing a system memory of the host system according to the memory access command; receiving data corresponding to the memory access command from the host system; and forwarding the received data to the local processor, wherein the system memory includes a secure area, access to which is allowed when the memory controller receives a memory access command from the local processor. In a feature of the present invention, there are provided a method and apparatus that can monitor integrity of data processed in the host system in a SoC environment.