OVERLAY CORRECTION METHOD, METHOD OF EVALUATING OVERLAY CORRECTION OPERATION, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE OVERLAY CORRECTION METHOD

    公开(公告)号:US20220179302A1

    公开(公告)日:2022-06-09

    申请号:US17392788

    申请日:2021-08-03

    Abstract: Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.

    EUV EXPOSURE APPARATUS, AND OVERLAY CORRECTION METHOD AND SEMICONDUCTOR DEVICE FABRICATING METHOD USING THE SAME

    公开(公告)号:US20210333701A1

    公开(公告)日:2021-10-28

    申请号:US16952844

    申请日:2020-11-19

    Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

    OVERLAY CORRECTION METHOD AND SEMICONDUCTOR FABRICATION METHOD INCLUDING THE SAME

    公开(公告)号:US20210116803A1

    公开(公告)日:2021-04-22

    申请号:US16886237

    申请日:2020-05-28

    Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

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