公开(公告)号：US20210116803A1

公开(公告)日：2021-04-22

申请号：US16886237

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Yong JUNG ,  Jinsun KIM ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG

IPC: G03F1/70 ,  G03F1/36 ,  H01L21/66 ,  H01L21/027 ,  G03F7/20

Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

公开(公告)号：US20250147409A1

公开(公告)日：2025-05-08

申请号：US18773908

申请日：2024-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Yong JUNG ,  Joon Hyun KIM ,  Seung Yoon LEE ,  Jeong Jin LEE ,  Chan HWANG

IPC: G03F1/42

Abstract: A method for manufacturing a semiconductor device includes providing a first pre-reticle including a first overlay mark and a first on-cell pattern. A second pre-reticle is provided that includes a second overlay mark and a second on-cell pattern. A first pattern is formed from the first pre-reticle using a first illumination system. A second pattern is formed from the second pre-reticle using a second illumination system. An overlay error is measured between the first pattern and the second pattern. A corrected reticle is formed based on the measured overlay error.

公开(公告)号：US20240061354A1

公开(公告)日：2024-02-22

申请号：US18233083

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hak PARK ,  Won Hyeok JO ,  Woo-Yong JUNG

IPC: G03F9/00 ,  G03F7/00 ,  G03F7/039

CPC classification number: G03F9/7088 ,  G03F7/70625 ,  G03F7/706849 ,  G03F7/70683 ,  G03F7/039

Abstract: A method of detecting coordinates of a mark is provided. The method includes: providing a plurality of structures and the mark on a wafer, each of the plurality of structures including a plurality of mold insulating layers and a plurality of mold sacrificial layers, which are alternately stacked, an end of each of the plurality of structures including a portion having a stair shape, and the mark being between adjacent structures among the plurality of structures; forming a photoresist layer on the plurality of structures and the mark, the photoresist layer including a portion concave toward the wafer between the adjacent structures; detecting the coordinates of the mark by irradiating a beam to the mark; determining an offset of the coordinates of the mark based on a beam path changing factor; and correcting the coordinates of the mark based on the offset.