公开(公告)号：US20160335185A1

公开(公告)日：2016-11-17

申请号：US15107255

申请日：2014-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok KWON ,  Chul-soo PARK ,  Suk-jin KIM

IPC: G06F12/0846 ,  G06F12/0815 ,  G06F12/0886

CPC classification number: G06F12/0851 ,  G06F12/0207 ,  G06F12/0815 ,  G06F12/0886 ,  G06F2212/621 ,  Y02D10/13

Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

Abstract translation: 存储器管理方法包括通过参考二维（2D）数据的大小来确定步幅访问的步幅值，并且将2D数据的垂直方向上的相邻数据分配给彼此不同的多个存储体 到确定的步幅值。 因此，可以通过使用具有大数据宽度的存储器来有效地访问垂直方向上的数据。

公开(公告)号：US20160188531A1

公开(公告)日：2016-06-30

申请号：US14757586

申请日：2015-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KWANGWOON UNIVERSITY INDUSTRY-ACADEMIC COLLABORATION FOUNDATION

Inventor： Young-hwan PARK ,  Hyunseok LEE ,  Yonggeun HONG ,  Suk-jin KIM

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/30036 ,  G06F9/3877

Abstract: An operation processing apparatus is provided. The operation processing apparatus includes a vector operator and cores. The vector operator processes a vector operation with respect to an instruction that uses the vector operation, and each core includes a scalar operator that processes a scalar operation with respect to an instruction that does not use the vector operation. The vector operator is shared by the cores.

Abstract translation: 提供了一种操作处理装置。 操作处理装置包括矢量运算器和核心。 向量运算符处理相对于使用向量运算的指令的向量运算，并且每个核心包括对与不使用向量运算的指令进行标量运算的标量运算符。 向量运算符由核心共享。

公开(公告)号：US20150227479A1

公开(公告)日：2015-08-13

申请号：US14619783

申请日：2015-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok KWON ,  Suk-jin KIM ,  Do-hyung KIM

IPC: G06F13/28

CPC classification number: G06F13/28 ,  Y02D10/14

Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

Abstract translation: 提供直接存储器访问（DMA）控制器。 DMA控制器包括：处理器接口，被配置为直接接收表示由处理器发送到缓冲器的第一操作的信息，并将对应于缓冲器中存储的第一操作的数据发送到处理器核心，或者记录对应于第一操作的数据 缓冲器和连接到处理器接口的缓冲器组，并且包括多个缓冲器。

公开(公告)号：US20140317383A1

公开(公告)日：2014-10-23

申请号：US14258640

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Un PARK ,  Suk-jin KIM

IPC: G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30178

Abstract: Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in the VLIW processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle; an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and an instruction converter configured to include the generated indicator code in the compressed instruction bundle.

Abstract translation: 提供了一种用于非常长的指令字（VLIW）处理器的指令压缩装置和方法，以及指令提取装置和方法。 指示压缩装置包括：指示符发生器，被配置为生成指示要在VLIW处理器中执行的指令束的发行宽度的指示符代码以及指令束之后的多个非操作（NOP）指令束; 指令压缩器，被配置为通过从所述指令束和所述指令束之后移除所述指令束和所述NOP指令束中的至少一个NOP指令来压缩所述指令束; 以及指令转换器，被配置为将生成的指示符代码包括在压缩指令束中。

公开(公告)号：US20190147319A1

公开(公告)日：2019-05-16

申请号：US16163772

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava PRASAD ,  Dae-hyun KIM ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06N3/04 ,  G06F17/15 ,  G06N5/04 ,  G06F12/06 ,  G06F21/52

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

公开(公告)号：US20190079779A1

公开(公告)日：2019-03-14

申请号：US16084906

申请日：2016-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-won LEE ,  Chae-seok IM ,  Seok-hwan JO ,  Suk-jin KIM

IPC: G06F9/445 ,  G06F9/30 ,  G06F9/50 ,  G06F8/41 ,  G06F12/0891

Abstract: A computing system is disclosed. The computing system according to one embodiment of the present disclosure comprises: a memory device for storing an application program; a processor for executing a loader for loading data of the application program into a memory space allocated for execution of the application program; a local memory having a width corresponding to the size of a register of the processor; and a constant memory having a width smaller than that of the local memory, wherein, according to the size of constant data included in the application program, the processor loads the constant data into one of the local memory and the constant memory.

公开(公告)号：US20180276532A1

公开(公告)日：2018-09-27

申请号：US15934341

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Ki-seok KWON ,  Suk-jin KIM ,  Chae-seok IM ,  Han-su CHO ,  Sang-bok HAN ,  Seung-won LEE ,  Kang-jin YOON

IPC: G06N3/04 ,  G06N3/063 ,  G10L15/16 ,  G06N99/00

CPC classification number: G06N3/0454 ,  G06N3/0445 ,  G06N3/063 ,  G06N20/00 ,  G10L15/16

Abstract: An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.

公开(公告)号：US20180067895A1

公开(公告)日：2018-03-08

申请号：US15697082

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Bernhard EGGER ,  Ho-chan LEE ,  Yeon-bok LEE ,  Suk-jin KIM

IPC: G06F15/78 ,  G06F9/30 ,  G06F12/06 ,  G06F9/445

CPC classification number: G06F15/7867 ,  G06F9/30 ,  G06F9/44505 ,  G06F12/0646 ,  G06F13/42 ,  G06F15/7871 ,  H03M7/30

Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.

公开(公告)号：US20170315811A1

公开(公告)日：2017-11-02

申请号：US15520168

申请日：2015-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok KWON ,  Min-wook AHN ,  Suk-jin KIM ,  Young-hwan PARK

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30087 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/34 ,  G06F9/3824

Abstract: Provided is a data processing method including the operations of storing, in a register, a first immediate portion included in a first instruction, from among the first immediate portion and a second immediate portion that constitute an immediate value, which is an operand; determining the immediate value by catenating the second immediate portion included in a second instruction with the stored first immediate portion; and performing an operation by using a value indicated by the second instruction and the determined immediate value.

公开(公告)号：US20170123658A1

公开(公告)日：2017-05-04

申请号：US15090111

申请日：2016-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Young-hwan PARK

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F12/00

Abstract: Methods and apparatuses for parallel processing data include reading items of data from a memory by using a memory access address, confirming items of data that have the same memory address from among the read items of data, masking items of data other than one from among the confirmed items of data, generating a correction value by using the confirmed items of data, performing an operation by using the items of data and the correction value, and storing, in the memory, data obtained by operating the data that has not been masked.