公开(公告)号：US12040391B2

公开(公告)日：2024-07-16

申请号：US17398407

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong Kim ,  Sunkyu Hwang ,  Jongseob Kim ,  Junhyuk Park

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66462

Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

公开(公告)号：US12002879B2

公开(公告)日：2024-06-04

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Joonyong Kim ,  Jongseob Kim ,  Junhyuk Park ,  Boram Kim ,  Younghwan Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Injun Hwang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/7787

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US11837642B2

公开(公告)日：2023-12-05

申请号：US17016877

申请日：2020-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soogine Chong ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Sunkyu Hwang ,  Injun Hwang

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L21/765 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/28587 ,  H01L21/765 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.